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检索条件"机构=The Computer Architecture for Embedded Systems"

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Multicore soc for on-board payload signal processing

Multicore soc for on-board payload signal processing

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NASA/ESA Conference on Adaptive Hardware and systems (AHS)

作者： Karel H.G. Walters S.H. Gerez G.J.M. Smit S. Baillou G.K. Rauwerda R. Trautner Computer Architecture for Embedded Systems University of Twente Enschede Netherlands Recore Systems Enschede Netherlands ESTEC European Space Agency Noordwijk Netherlands

This paper introduces a new generic platform for onboard payload signal processing. The system is built up around an NoC with a bridge to an AMBA system which supports easy integration with existing AMBA based platforms. With the use of a pthreads interface the platform allows for simple programming and easy extension. For prototyping purposes, an implementation has been made on an FPGA together with a range of I/O options to assess its capabilities. SpaceWire and other interfaces support the extension of the demonstrator platform across multiple boards and allow to connect it to onboard networks and systems. This paper shows that novel and established chip architectures can be integrated in a way that combines their benefits, and represents a promising candidate architecture for future on-board processing platforms.

关键词： Europe Field programmable gate arrays Multicore processing Switches Kernel Wavelet transforms

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GPU vs FPGA: Example Application on White Light Interferometry

GPU vs FPGA: Example Application on White Light Interferomet...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： A. Pacholik M. Muller W. Fengler T. Machleidt K.-H. Franke Computer Architecture and Embedded Systems Group Ilmenau University of Technology Ilmenau Germany Computer Graphics Group Ilmenau University of Technology Ilmenau Germany

High performance image processing applications area challenging field when targeting embedded processing. Field programmable gate arrays (FPGA) receive a growing interest as implementation platforms, but these solutions have to compete with the state of the art in image processing, which is codefined by graphics processing units (GPU). This paper provides a case study which analyzes the potential of embedded or hybrid implementation on FPGA and GPU for image stack processing in a white light interferometry (WLI) application.

关键词： Graphics processing unit Field programmable gate arrays Demodulation Image resolution Bandwidth Throughput Hardware

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Towards safe data flow processing by integration of design by contract in deterministic UML activities

Towards safe data flow processing by integration of design b...

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Zamira Daw Marcus Vetter Josef Boercsoek Institute of Embedded Systems Hochschule Mannheim-University of Applied Sciences Mannheim Germany Department of Computer Architecture and System Programming University of Kassel Kassel Germany

Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime.

关键词： Unified modeling language Contracts Monitoring embedded systems Object oriented modeling Safety Pins

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Functional Framework and Hardware Platform for Dependability Study in Short Range Wireless embedded systems

Functional Framework and Hardware Platform for Dependability...

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IEEE International Mixed-Signals, Sensors, and systems Test Workshop, IMS3TW

作者： Benaouneur Senouci Anne-Johan Annema Mark Bentum Hans G. Kerkhoff Telecommunication Engineering Group Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group University of Twente Enschede Netherlands Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and at different abstractions levels. This paper presents a hardware platform for wireless system dependability analysis as an alternative for the time consuming global system simulation technique. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed methodology are two fold: first it takes care of the whole system (HW/SW part, mixed RF and wireless part) and second, the hardware platform enables to explore the application's reliability under real environmental conditions in order to study the effect of the environment threats on the system.

关键词： Wireless communication Hardware Reliability System-on-a-chip computer architecture Libraries embedded systems

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Towards dependability-aware design of hardware systems using extended program state machines

Towards dependability-aware design of hardware systems using...

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2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORCW 2011

作者： Grüttner, Kim Herrholz, Andreas Kühne, Ulrich Große, Daniel Rettberg, Achim Nebel, Wolfgang Drechsler, Rolf OFFIS - Institute for Information Technology HW/SW Design Methodology Group Oldenburg Germany CoSynth GmbH and Co. KG Oldenburg Germany LSV ENS de Cachan Cachan France University of Bremen Group for Computer Architecture Bremen Germany Carl Von Ossietzky University Oldenburg Embedded Hardware/Software Systems Oldenburg Germany

ISBN: (纸本)9780769543772

Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embedded systems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embedded systems has to change fundamentally. Therefore, we propose a dependability-aware design approach for hardware systems through integrating dependability into a state-of-the-art system-level design language. Our approach is based on SystemC and extends the Program State Machine model to explicitly observe, diagnose, and compensate faulty behavior. Different compensation mechanisms like run-time reconfiguration or mechanisms for error propagation can be used by the designer during refinement. They are controlled by a new exception-like mechanism. Furthermore, our approach aims to integrate functional verification as well as dependability verification with respect to given fault models. © 2011 IEEE.

关键词： embedded systems

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Towards Dependability-Aware Design of Hardware systems Using Extended Program State Machines

Towards Dependability-Aware Design of Hardware Systems Using...

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IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW)

作者： Kim Gruttner Andreas Herrholz Ulrich Kuhne Daniel Grosse Achim Rettberg Wolfgang Nebel Rolf Drechsler HW/SW Design Methodology Group OFFIS Institute of Information Technology Oldenburg Germany CoSynth GmbH and Company KG Oldenburg Germany LSV ENS de Cachan Cachan France Group for Computer Architecture University of Brethemen Bremen Germany Embedded Hardware/Software Systems Carl von Ossietzky University슠of슠Oldenburg Oldenburg Germany

关键词： Computational modeling Hardware Circuit faults computer architecture Fault tolerance Switches Adaptation model

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A 50MHz-to-1.5GHz cross-correlation CMOS spectrum analyzer for cognitive radio with 89dB SFDR in 1MHz RBW

A 50MHz-to-1.5GHz cross-correlation CMOS spectrum analyzer f...

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2010 IEEE Symposium on New Frontiers in Dynamic Spectrum, DySPAN 2010

作者： Oude Alink, Mark S. Klumperink, Eric A. M. Soer, Michiel C. M. Kokkeler, André B. J. Nauta, Bram Integrated Circuit Design/Computer Architecture for Embedded Systems CTIT Research Institute University of Twente Enschede Netherlands

ISBN: (纸本)9781424451883

关键词： Spectrum analyzers

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C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell

C?aSH: Structural Descriptions of Synchronous Hardware Using...

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Euromicro Symposium on Digital System Design

作者： Christiaan Baaij Matthijs Kooijman Jan Kuper Arjan Boeijink Marco Gerards Computer Architecture for Embedded Systems (CAES) Department of EEMCS University of Twente Enschede Netherlands

CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higher-order functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements found in the traditional hardware description languages. Circuit descriptions can be translated to synthesizable VHDL using the prototype CλaSH compiler. As the circuit descriptions, simulation code, and test input are also valid Haskell, complete simulations can be done by a Haskell compiler or interpreter, allowing high-speed simulation and analysis.

关键词： Hardware Integrated circuit modeling Pattern matching Hardware design languages Multiplexing Prototypes Radiation detectors

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A 50Mhz-To-1.5Ghz Cross-Correlation CMOS Spectrum Analyzer for Cognitive Radio with 89dB SFDR in 1Mhz RBW

A 50Mhz-To-1.5Ghz Cross-Correlation CMOS Spectrum Analyzer f...

引用

IEEE International Symposium on New Frontiers in Dynamic Spectrum Access Networks, DySPAN

作者： Mark S. Oude Alink Eric A. M. Klumperink Michiel C. M. Soer Andre B. J. Kokkeler Bram Nauta Integrated Circuit Design / Computer Architecture for Embedded Systems CTIT Research Institute University of Twente Enschede Netherlands

Spectrum sensing for cognitive radio requires a high linearity to handle strong signals, and at the same time a low noise figure (NF) to enable detection of much weaker signals. Often there is a trade-off between linearity and noise: improving one of them degrades the other. Cross-correlation can break this trade-off by reducing noise at the cost of measurement time. An existing RF front-end in CMOS-technology with IIP3=+11dBm and NF<6.5dB is duplicated and attenuators are put in front to increase linearity (IIP3=+24dBm). The attenuation degrades NF, but by using cross-correlation of the outputs of the two frontends, the NF is reduced to below 4dB. In total this results in a spurious-free dynamic range (SFDR) of 89dB in 1MHz resolution bandwidth (RBW).

关键词： Spectral analysis Cognitive radio Noise measurement Linearity Degradation Noise figure Noise reduction Costs Time measurement Radio frequency

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Simulation of High-Performance Memory Allocators

Simulation of High-Performance Memory Allocators

引用

Euromicro Symposium on Digital System Design

作者： Jose L. Risco-Martín J. Manuel Colmenar David Atienza J. Ignacio Hidalgo Dept. of Computer Architecture and Automation Complutense University of Madrid Madrid Spain C.E.S. Felipe II Complutense University of Madrid Aranjuez Spain Embedded Systems Laboratory (ESL) EPFL Lausanne Switzerland

Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern high-performance applications. To optimize metrics like performance, memory usage and energy consumption, software engineers often write custom allocators from scratch, which is a difficult and error-prone process. In this paper, we present a flexible and efficient simulator to study Dynamic Memory Managers (DMMs), a composition of one or more memory allocators. This novel approach allows programmers to simulate custom and general DMMs, which can be composed without incurring any additional runtime overhead or additional programming cost. We show that this infrastructure simplifies DMM construction, mainly because the target application does not need to be compiled every time a new DMM must be evaluated. Within a search procedure, the system designer can choose the "best" allocator by simulation for a particular target application. In our evaluation, we show that our scheme will deliver better performance, less memory usage and less energy consumption than single memory allocators.

关键词： Memory management Resource management Energy consumption Dynamic scheduling Software Computational modeling Algorithm design and analysis

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