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Euromicro Symposium on Digital System Design

作者： Christiaan Baaij Matthijs Kooijman Jan Kuper Arjan Boeijink Marco Gerards Computer Architecture for Embedded Systems (CAES) Department of EEMCS University of Twente Enschede Netherlands

CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higher-order functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements found in the traditional hardware description languages. Circuit descriptions can be translated to synthesizable VHDL using the prototype CλaSH compiler. As the circuit descriptions, simulation code, and test input are also valid Haskell, complete simulations can be done by a Haskell compiler or interpreter, allowing high-speed simulation and analysis.

关键词： Hardware Integrated circuit modeling Pattern matching Hardware design languages Multiplexing Prototypes Radiation detectors

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Multi-domain transformational design flow for embedded systems

Multi-domain transformational design flow for embedded syste...

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International Conference on embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Kenneth C. Rovers Marcel D. van de Burgwal Jan Kuper André B. J. Kokkeler Gerard J. M. Smit Computer Architecture for Embedded Systems group CTIT Department of EEMCS University of Twente Enschede Netherlands

Current tools for embedded system design have limited support for modelling the interaction of the system with its physical environment. Furthermore, the natural representation of (streaming, real-time) applications with dataflow models is not supported by most tools. However, integrating multiple domains supports the design of complex interdisciplinary systems and enables model transformations. In this paper we discuss a unified approach, called UniTi, to handle continuous and discrete time models in a single framework, which includes the dataflow model as well. Our approach consists of a transformational design flow, expressed mathematically in a functional language. We formally distinguish the various domains and explain their interaction. In addition, we give guidelines for specifying algorithms such that these transformations can be applied. Our approach is illustrated with a non-trivial case study: beamforming in a phased array system.

关键词： Mathematical model Hardware Parallel processing computer architecture embedded systems Delay

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Adaptive resource allocation for streaming applications

Adaptive resource allocation for streaming applications

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International Conference on embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Timon D. ter Braak Hermen A. Toersche André B. J. Kokkeler Gerard J. M. Smit Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Enschede Netherlands

Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time.

关键词： Hardware Routing Resource management Global Navigation Satellite systems Receivers Tiles Radio frequency

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Fusion Model Using a Neural Network and MLE for a Single Snapshot DOA Estimation with Imperfection Mitigation

Fusion Model Using a Neural Network and MLE for a Single Sna...

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IEEE International Conference on Radar

作者： Marcio L. Lima De Oliveira Marco J. G. Bekooij Computer Architecture for Embedded Systems University of Twente Enschede The Netherlands Department of Embedded Software and Signal Processing NXP Semiconductors University of Twente Eindhoven The Netherlands

In this paper, we discuss the fusion of deep neural networks with the Maximum Likelihood Estimation (MLE) algorithm for estimating both the Direction Of Arrival (DOA) of MIMO radars and the number of sources for a single-snapshot scenario using a Minimum Redundancy antenna Array (MRA) with imperfections and evaluating it with synthetic and real-world data. The combination of Deep Learning (DL) with the classical MLE seems to be a viable solution for this problem, as it is less computationally intensive than a classical MLE while not losing generalization and being better at estimating the number of sources. In both our experiments, using synthetic and real-world data, our method performs close to MLE and appears to be a deployable solution for real scenarios. Besides reducing the computational load of MLE, the novelty of our model lies in the fact that the deep learning model learns the gain and phase errors as a function of the direction of arrival instead of applying a simple calibration.

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Minimizing peak power for application chains on architectures with partial dynamic reconfiguration

Minimizing peak power for application chains on architecture...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Sudarshan Banerjee Elaheh Bozorgzadeh Juanjo Noguera Nikil Dutt Center for Embedded Computer Systems University of California Irvine CA USA Department of Computer Architecture Technical University of Catalonia Barcelona Spain

Power consumption is a key concern on modern reconfigurable architectures. In this paper, we address the problem of minimizing peak power while mapping application task chains onto reconfigurable architectures with partial dynamic reconfiguration capability. Our proposed methodology minimizes peak power for a given timing constraint. It is based on detailed data-parallelism considerations to ensure that tight timing constraints are met. Our methodology generates physically placed task execution schedules and includes selection of a suitable number of data-parallel instances for each task, a suitable clock frequency, and execution workload for each task instance. Case studies on real image-filtering applications demonstrate that our approach results in significant peak power savings (between 40%-50%) for tight as well as relaxed timing constraints

关键词： Timing Energy consumption Reconfigurable architectures Application software computer architecture Frequency Runtime Hardware Logic devices Reconfigurable logic

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Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable architectures 07

Selective Band width and Resource Management in Scheduling f...

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Design Automation Conference

作者： Sudarshan Banerjee Elaheh Bozorgzadeh Nikil Dutt Juanjo Noguera Center for Embedded Computer Systems University of California Irvine CA USA Department of Computer Architecture Technical University of Catalonia Barcelona Spain

ISBN: (纸本)9781595936271

Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources such as data bandwidth, configurable logic, and the limited logic resources are customized during application execution with partial RTR. In this work, we present key theoretical principles for maximizing application performance when available bandwidth is limited. We exploit bandwidth very effectively by selecting a suitable clock frequency for each task and maximize performance with partial RTR by exploiting data-parallelism property of common image-processing tasks. Our theoretical principles are integrated in our scheduling strategy, SCHEDRTR. We present detailed application case studies on a cycle-accurate simulation platform that addresses microarchitectural concerns and includes detailed resource considerations of the Virtex XC2V3000 device. Our results demonstrate that applying SCHEDRTR to common image-filtering applications leads to 15-20% performance gain in scenarios with limited bandwidth, when compared to a sophisticated RTR scheduling strategy with data-parallelism but simpler bandwidth considerations.

关键词： Resource management Dynamic scheduling Reconfigurable architectures Bandwidth Reconfigurable logic Processor scheduling Clocks Frequency Microarchitecture Performance gain

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A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

TechRxiv

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TechRxiv 2023年

作者： Menbari, Ahmad Rahimi, Hemin Jahanirad, Hadi Ziener, Daniel The Department of Electrical Engineering University of Kurdistan Sanandaj Iran The Department of Computer Architecture and Embedded Systems Ilmenau University of Technology Ilmenau Germany

In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitates robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. © 2023, CC BY.

关键词： Built-in self test

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Towards safe data flow processing by integration of design by contract in deterministic UML activities

Towards safe data flow processing by integration of design b...

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Zamira Daw Marcus Vetter Josef Boercsoek Institute of Embedded Systems Hochschule Mannheim-University of Applied Sciences Mannheim Germany Department of Computer Architecture and System Programming University of Kassel Kassel Germany

Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime.

关键词： Unified modeling language Contracts Monitoring embedded systems Object oriented modeling Safety Pins

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Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC

arXiv

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arXiv 2024年

作者： Rogenmoser, Michael Wiese, Philip Forlin, Bruno Endres Gürkaynak, Frank K. Rech, Paolo Menicucci, Alessandra Ottavi, Marco Benini, Luca The Integrated Systems Laboratory ETH Zurich Switzerland The Computer Architecture for Embedded Systems The University of Twente Netherlands The Department of Industrial Engineering The University of Trento Italy The Department of Space Engineering The Delft University of Technology Netherlands The Computer Architecture for Embedded Systems The University of Twente Netherlands The Department of Electronic Engineering The University of Rome Tor Vergata Italy The Integrated Systems Laboratory ETH Zurich Switzerland The Department of Electrical Electronic and Information Engineering The University of Bologna Italy

We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteein... 详细信息

关键词： Fault tolerance

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VersaSens: An Extendable Multimodal Platform for Next-Generation Edge-AI Wearables

IEEE Transactions on Circuits and Systems for Artificial Int...

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IEEE Transactions on Circuits and systems for Artificial Intelligence 2024年第1期1卷 83-96页

作者： Taraneh Aminosharieh Najafi José Angel Miranda Calero Jérôme Thevenot Benjamin Duc Stefano Albini Alireza Amirshahi Hossein Taji María José Belda Beneyto Antonio Affanni David Atienza Embedded Systems Laboratory (ESL) Institute of Electrical and Micro Engineering École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland Polytechnic Department of Engineering and Architecture Udine Italy Computer Architecture and Automation Department Universidad Complutense de Madrid Madrid Spain

The transition of healthcare towards digitalization is closely related to the advancement of health-related technologies, including wearable sensors and edge computing. In this paper, we present VersaSens, a versatile and customizable platform concept and its real implementation as a tool to boost research in wearable sensors. The platform embodies the core attributes of the VersaSens concept: versatility, flexibility, and extendability across multiple aspects of hardware, software, and processing components. It features a modular design, consisting of sensor, processor, and co-processor modules, allowing for various configurations. To evaluate the efficiency of the platform, we tested three use cases: cough monitoring, heartbeat classification and epileptic seizure detection. In all cases, the results indicate that the platform effectively executes the applications, achieving low energy consumption. In particular, our findings indicates that the integration of a domain-specific edge-AI co-processor [i.e., HEEP ocrates (Machetti et al., 2024)] equipped with several hardware accelerators further improved the overall execution time and energy consumption of the system. These results demonstrate the potential of VersaSens to effectively support a diverse range of edge-AI applications and configurations, thereby providing a robust foundation for the research and development of novel smart wearable sensor systems.

关键词： Sensors Wearable devices Artificial intelligence Wearable sensors Medical services Intelligent sensors Monitoring

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