Three-dimensional (3D) circuits reduce communication delay in multicore SoCs, and enable efficient integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the relia...
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Three-dimensional (3D) circuits reduce communication delay in multicore SoCs, and enable efficient integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the reliability and thermal problems, and cooling efficiency becomes a limiting factor. Liquid cooling is a solution to overcome the accelerated thermal problems imposed by multi-layer architectures. In this paper, we first provide a 3D thermal simulation model including liquid cooling, supporting both fixed and variable fluid injection rates. Our model has been integrated in HotSpot to study the impact on multicore SoCs. We design and evaluate several dynamic management policies that complement liquid cooling. Our results for 3D multicore SoCs, which are based on 3D versions of UltraSPARC T1, show that thermal management approaches that combine liquid cooling with proactive task allocation are extremely effective in preventing temperature problems. Our proactive management technique provides an additional 75% average reduction in hot spots in comparison to applying only liquid cooling. Furthermore, for systems capable of varying the coolant flow rate at runtime, our feedback controller increases the improvement to 95% on average.
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to ...
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ISBN:
(纸本)9783981080155
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.
Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources such as data bandwidth, configurable logic, and the limited ...
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ISBN:
(纸本)9781595936271
Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources such as data bandwidth, configurable logic, and the limited logic resources are customized during application execution with partial RTR. In this work, we present key theoretical principles for maximizing application performance when available bandwidth is limited. We exploit bandwidth very effectively by selecting a suitable clock frequency for each task and maximize performance with partial RTR by exploiting data-parallelism property of common image-processing tasks. Our theoretical principles are integrated in our scheduling strategy, SCHEDRTR. We present detailed application case studies on a cycle-accurate simulation platform that addresses microarchitectural concerns and includes detailed resource considerations of the Virtex XC2V3000 device. Our results demonstrate that applying SCHEDRTR to common image-filtering applications leads to 15-20% performance gain in scenarios with limited bandwidth, when compared to a sophisticated RTR scheduling strategy with data-parallelism but simpler bandwidth considerations.
Power consumption is a key concern on modern reconfigurable architectures. In this paper, we address the problem of minimizing peak power while mapping application task chains onto reconfigurable architectures with pa...
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Power consumption is a key concern on modern reconfigurable architectures. In this paper, we address the problem of minimizing peak power while mapping application task chains onto reconfigurable architectures with partial dynamic reconfiguration capability. Our proposed methodology minimizes peak power for a given timing constraint. It is based on detailed data-parallelism considerations to ensure that tight timing constraints are met. Our methodology generates physically placed task execution schedules and includes selection of a suitable number of data-parallel instances for each task, a suitable clock frequency, and execution workload for each task instance. Case studies on real image-filtering applications demonstrate that our approach results in significant peak power savings (between 40%-50%) for tight as well as relaxed timing constraints
While having the simple task of gathering the most basic information, wireless sensor networks can pose very complex design challenges because of the limited quantity of resources available. The (often too complex) pr...
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ISBN:
(纸本)0976798522
While having the simple task of gathering the most basic information, wireless sensor networks can pose very complex design challenges because of the limited quantity of resources available. The (often too complex) protocols needed to assure the quality and the amount of needed data are usually hard to implement in the target hardware. The aim of this paper is to present a new architecture more suited for the wireless sensor networks than what is already available. The new architecture is designed to suit the dynamic environments in which these systems will be deployed.
This volume contains the papers and posters selected for presentation at the First European Conference on Smart Sensing and Context (EuroSSC 2006) in Enschede, The Netherlands. EuroSSC 2006 was the ?rst conference of ...
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ISBN:
(数字)9783540478454
ISBN:
(纸本)9783540478423
This volume contains the papers and posters selected for presentation at the First European Conference on Smart Sensing and Context (EuroSSC 2006) in Enschede, The Netherlands. EuroSSC 2006 was the ?rst conference of a series aiming at bringing together designers, engineers and researchers to explore two complementary viewpoints: – A device-centric,technology-drivenview: concerning intelligent sensors,s- sor networks and information processing for a new generation of networked devices and environments. – A service-centric, user-driven view: exploring architectures, techniques, and algorithms for context-aware and pro-active applications made possible by thedi?usionofambientcommunication,cooperatingobjects,andinteraction technologies. These subjects are active and relevant research areas in themselves, and there are several conferences that address them separately. EuroSSC 2006, however, considered them both, and especially the symbiosis between them, which we expect to result in very inspiring and interesting discussions, as well as new research ideas on how to combine them. The conference was organized in single tracks covering various issues ra- ing from intelligent sensors, sensor networks, context management and context awareness,andprivacy,toapplicationsandtestbeds. Organizingaconferencefor the ?rst time requires lots of preparations, such as ?nding a publisher, spons- ing organizations,and TPC members and most importantly attracting potential submitters. Fortunately, the amount and quality of the submissions were such that we were in the luxurious position to be able to accept only high quality and relevant papers. The conference attracted world wide attention and submissions came from ?ve continents. A total of 15 accepted full papers and 14accepted posters came from Asia, North America and Europe.
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