检索结果-内蒙古大学图书馆

A Graph Model for Fault-Tolerant Computing Systems

IEEE Transactions on computers 1976年第9期C-25卷 875-884页

作者： Hayes, John P. Department of Electrical Engineering Computer Science Program University of Southern California Los Angeles CA 90007 United States

An approach to fault-tolerant design is described in which a computing system S and an algorithm A to be executed by S are both defined by graphs whose nodes represent computing facilities. A is executable by S if A is isomorphic to a subgraph of S. A k-fault is the removal of k nodes (facilities) from S. S is a k-faulttolerant (k-FT) realization of A if A can be executed by S with any k-fault present in S. The problem of designing optimal k-FT systems is considered where A is equated to a 0-FT system. Techniques are described for designing optimal k-FT realizations of single-loop systems;these techniques are related to results in Hamiltonian graph theory. The design of optimal k-FT realizations of certain types of tree systems is also examined. The advantages and disadvantages of the graph model are discussed. Copyright © 1976 by The Institute of electrical and Electronics Engineers, Inc.

关键词： computer architecture fault-tolerant computing fault-tolerant design graph theory Hamiltonian graphs singleloop systems tree systems

来源：评论

学校读者我要写书评

暂无评论

On the Properties of Irredundant Logic Networks

引用

IEEE Transactions on computers 1976年第9期C-25卷 884-892页

作者： Hayes, John P. Department of Electrical Engineering Computer Science Program University of Southern California Los Angeles CA 90007 United States

The constraints imposed by various types of irredundancy on the structure of combinational logic networks are investigated. It is shown that the usual notion ofirredundancy here called a-irredundancy, places bounds on the maximum number of inputs to certain types of network structures. A network is called b-redundant if it contains a cascade of single-input gates that can be reduced to either an inverter or a single line. Let Nab(Z) denote all realizations of Z that are both a - and b-irredundant. If N E Nab(Z), then the number of gates in any fan-out-free subnetwork of N is bounded. It is shown that a solution to some important design optimization problems can be found in Nab(Z). It is conjectured that Nab(Z) is finite and some results supporting this conjecture are presented. For example, it is impossible to construct an arbitrarily long cascade of networks that perform the identity transformation without introducing a-or b-redundancy. A more general type of redundancy, c-redundancy, is defined which includes both a-and b-redundancy as special cases. The class of c-irredundant realizations of Z is finite. Copyright © 1976 by The Institute of electrical and Electronics Engineers, Inc.

关键词： Combinational networks irredundant networks logic circuits logic design optimization redundancy redundancy testing redundancy types

来源：评论

学校读者我要写书评

暂无评论

A Dynamic Database Reorganization Algorithm

引用

ACM Transactions on Database Systems (TODS) 1976年第2期1卷 159-174页

作者： Yao, S.B. Das, K.S. Teorey, T.J. Department of Computer Sciences Purdue University West Lafayette IN 47907 United States Department of Electrical and Computer Engineering Program in Computer Information and Control Engineering (CICE) University of Michigan Ann Arbor MI 48109 United States

Reorganization is necessary in some databases for overcoming the performance deterioration caused by updates. The paper presents a dynamic reorganization algorithm which makes the reorganization decision by measuring the database search costs. Previously, the reorganization intervals could only be determined for linear deterioration and known database lifetime. It is shown that the dynamic reorganization algorithm is near optimum for constant reorganization cost and is superior for increasing reorganization cost. In addition, it can be applied to cases of unknown database lifetime and nonlinear performance deterioration. The simplicity, generality, and efficiency appear to make this good heuristic for database reorganization. © 1976, ACM. All rights reserved.

关键词： database file organization information retrieval reorganization

来源：评论

学校读者我要写书评

暂无评论

A Flexible Renewal Process Simulator for Neural Spike Trains

引用

IEEE Transactions on Biomedical engineering 1976年第3期BME-23卷 262-266页

作者： Belanger, Barry F. Williams, William J. Yin, Tom C. T. Bioelectrical Sciences Laboratory Department of Electrical and Computer Engineering and the Bioengineering Program University of Michigan Ann Arbor MI 48109. United States

Certain neuronal spike trains may be viewed as stochastic, nonhomogeneous point process. Neuronal information may be encoded in the time-varying mean rate of the spike train in some cases. For this purpose the simulat... 详细信息

关键词： Humans Heart Bioelectric phenomena Testing Cardiology Myocardium Neurons Laboratories Thorax Signal analysis

来源：评论

学校读者我要写书评

暂无评论

The Viterbi Algorithm as an Aid in Text Recognition

引用

IEEE Transactions on Information Theory 1975年第2期21卷 222-226页

作者： Neuhoff, David L. Electrical Engineering Department Stanford University Department of Electrical and Computer Engineering Computer Information and Control Engineering Program University of Michigan Stanford Calif. Ann Arbor Mich. United States

The results of an experiment are described in which contextual information is used to improve the performance of an optical character reader when reading English text. Specifically, English is modeled as a Markov source and the Viterbi algorithm is used to do maximum a posteriori sequence estimation on the output of an optical character reader (OCR). © 1975 IEEE. All rights reserved.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Higher radix, non-restoring division: History and recent developments 3

Higher radix, non-restoring division: History and recent dev...

引用

3rd Symposium on computer Arithmetic, ARITH 1975

作者： Atkins, Daniel E. Department of Electrical and Computer Engineering Program in Computer Information and Control Engineering The University of Michigan Ann ArborMI48104 United States

来源：评论

学校读者我要写书评

暂无评论

An educational laboratory in contemporary digital design 2

An educational laboratory in contemporary digital design

引用

2nd Annual Symposium on computer Architecture, ISCA 1975

作者： Baron, Janis Beitch Atkins, D.E. Department of Electrical and Computer Engineering Program in Computer Information and Control Engineering University of Michigan Ann ArborMI48104 United States

Formal education in computer architecture rests upon the integration of numerous specialized courses. One such course, a new laboratory concerning contemporary, register-transfer level digital design, is described. Design in the course proceeds at the level of interconnection of memories, arithmetic logic units, I/O interfaces, and buses, rather than at the individual gate level associated with traditional combinational and sequential logic design. The principle items of hardware used in the laboratory are DEC Register Transfer Modules, the DEC PDP/16M, and the INTEL SIM8-01 Microcomputer. Numerous software packages have been developed to support activities within the lab including an RTM simulator, a graphical simulation of an RTM control sequencer, a PDP/16M assembler, a microcode generator, and SIM8-01 utility routine, assembler, and simulator. During one fourteen-week term, students are expected to complete six assigned lab projects and one special project. Examples of projects are described. A critique based upon the students' reactions and the technician's experience with the equipment is given together with proposals for future additions to the course. © 1974 Authors.

关键词： Students

来源：评论

学校读者我要写书评

暂无评论

Optimal Placement of Software Monitors Aiding Systematic Testing

引用

IEEE Transactions on Software engineering 1975年第4期SE-1卷 403-411页

作者： Ramamoorthy, C.V. Kim, K.H. Chen, W.T. Computer Science Division Department of Electrical Engineering and Computer Sciences University of California Berkeley Calif 94720 United States Department of Electrical Engineering Systems and Computer Science Program University of Southern California Los Angeles Calif. United States

The usefulness of software monitors in testing large ‘programs is discussed. Several types of testing strategies based on the use of monitors are surveyed. Since there is a computational overhead involved in employing monitors, attempts are made to minimize the number of monitors employed. This optimization problem is formulated and analyzed in graph-theoretic terms. Implementation aspects are considered through both discussion and examples. Copyright © 1975 by The Institute of electrical and Electronics Engineers, Inc.

关键词： Optimal placement overhead program testing software monitor test-input test-output test-path test-run

来源：评论

学校读者我要写书评

暂无评论

The Fanout Structure of Switching Functions

引用

Journal of the ACM (JACM) 1975年第4期22卷 551-571页

作者： Hayes, John P. Department of Electrical Engineering and Computer Science Program University of Southern California Los Angeles CA 90007 United States

The problem of determining the amount of fanout required to reahze a switching function m investigated. The significance of fanout in switching networks is discussed Fanout-free functions are introduced and their propertms examined. Two relations, adjacency and masking, are defined on the variables X of a functlon f(X), and these relations are used to characterize fanoutfree functions A quantity τ(f) called the input fanout index of f is defined for arbitrary switching functions;τ(f) represents the minimum number of input variables that require fanout in any reahzation of ff It is shown that τ(f) can be determined from the pmme lmphcants and prime imphcates of f using two additmnal relations on X, the conjugate property and compatibility An algorithm is presented for finding a reahzatlon of f in whmh only τ(f) variables fan out. Some other measures of fanout are briefly considered. © 1975, ACM. All rights reserved.

关键词： fanout fanout-free functions fanout-free networks Input fanout index mimmlzatlon of fanout partially fanout-free functtons switching functions

来源：评论

学校读者我要写书评

暂无评论

Linear algorithms to recognize interval graphs and test for the consecutive ones property 75

Linear algorithms to recognize interval graphs and test for ...

引用

7th Annual ACM Symposium on Theory of Computing, STOC 1975

作者： Booth, Kellogg S. Lueker, George S. Department of Electrical Engineering and Computer Sciences University of California Berkeley United States Lawrence Livermore Laboratory United States Department of Electrical Engineering and Program in Applied Mathematics Princeton University United States

ISBN: (纸本)9781450374194

A matrix of zeroes and ones is said to have the consecutive ones property if there is a permutation of its rows such that the ones in each column appear consecutively. This paper develops a data structure which may be used to test a matrix for the consecutive ones property, and produce the desired permutation of the rows, in linear time. One application of the consecutive ones property is in recognizing interval graphs. A graph is an interval graph if there exists a i-i correspondence between its vertices and a set of intervals on the real line such that two vertices are adjacent if and only if the corresponding intervals have a nonempty intersection. Fulkerson and Gross have characterized interval graphs as those for which the clique versus vertex incidence matrix has the consecutive ones property. In testing this particular matrix for the consecutive ones property we may process the columns in a special order to simDlifv the algorithm. This yields the interval graph recognition algorithm which is presented in section 2;section 3 indicates how this algorithm may be extended to the general consecutive ones problem. A final section of the paper gives a number of further applications of the ideas developed in the earlier sections. These applications include linear algorithms to a) recognize unit interval graphs, b) test for the circular ones property, c) recognize planar graphs, d) count the number of distinct models of an interval graph (assuming that an arithmetic operation can be done in constant time), and e) determine whether two interval graphs are isomorphic. © 1975 Association for Computing Machinery. All rights reserved.

关键词： Matrix algebra

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：