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Solving the FPGA Routing Problem Using the Model of an Extended Mixed Routing Graph

russian microelectronics 2023年第7期52卷 682-689页

作者： Zapletina, M.A. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia

Abstract: An architecture-aware extended mixed routing graph model allows describing the features of the routing resources of modern field-programmable gate arrays (FPGA). It can be used to solve the tasks of interconnections routing as part of an FPGA layout synthesis flow. In this work, an architecture-aware extended mixed routing graph model is considered. Two modifications are proposed for the basic method of automatic routing that is the classical Pathfinder algorithm adapted to a mixed routing resources graph. The first modification is based on the idea of a directed search on the graph model using data on the spatial and geometric characteristics of the basic FPGA chip, while the second one combines a directed search strategy with consideration of a preliminary routing congestion assessment based on the results of the placement procedure. It has been demonstrated that the proposed modifications make it possible to accelerate the basic method convergence by an average of 50.6 and 38.6%, respectively. While maintaining the routability of IWLS’2005, ISCAS’89 and LGSynth’89 benchmark suits, the use of only directed search led to an improvement in the timing characteristics of test circuits implementations by 5.2% on average, and its use together with an assessment of congestion before the start of routing, to these characteristics improvement by 9.3% on average relative to the results of the basic Pathfinder method. © Pleiades Publishing, Ltd. 2023. ISSN 1063-7397, russian microelectronics, 2023, Vol. 52, No. 7, pp. 682–689. Pleiades Publishing, Ltd., 2023. russian Text The Author(s), 2022, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2022, Vol. 27, No. 6, pp. 774–786.

关键词： Field programmable gate arrays (FPGA)

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Dynamics of the Vector of Magnetization in a Free Layer of a Spin Valve with Planar Anisotropy under the Action of Arbitrarily Directed Magnetic Fields

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Bulletin of the russian Academy of Sciences: Physics 2023年第3期87卷 310-317页

作者： Iusipova, Iu. A. Skidanov, V.A. Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia

Abstract: Modeling is done for the dynamics of the vector of magnetization in the free layer of a spin valve with planar layer anisotropy in arbitrarily directed magnetic fields. Bifurcation analysis of the dynamic system, the conditions for changing the type of singular points are established, and the dynamics of magnetization is classified. © 2023, Allerton Press, Inc.

关键词： Magnetization

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Formation of IP-Core Libraries in the User IC design Flow for FPGAs and RSoCs

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russian microelectronics 2022年第7期51卷 567-572页

作者： Khvatov, V.M. Gavrilov, S.V. Institute for Design Problems in Microelectronics of the Russian Academy of Sciences Moscow Russia

Abstract: Complex functional blocks or intellectual property (IP) cores are developed and used to speed up the user IC design flow and improve their final characteristics. There are two IP-cores types—soft IP-cores and hard IP-cores. A hard IP core has a fixed on-chip layout and pre-routed interconnects, while a soft IP core consists of logic gates and requires placement and routing. For an automated flow for designing ICs based on FPGAs and reconfigurable systems on a chip (RSoC) it is necessary to develop core libraries that allow them to be identified at each stage of the design flow. The paper shows various types and formats of libraries of soft and hard IP-cores used in the design flow for ICs based on FPGAs and russian-made RSoCs. Methods for designing libraries of necessary CAD systems at the stages of logical synthesis, automatic technological mapping and layout synthesis are described. The characteristic features of soft and hard IP-cores libraries, as well as methods for their formation, are considered taking into account the architecture of FPGAs and RSoCs. The proposed design methods make it possible to develop libraries that are necessary for the automated implementation of all types of IP-cores, taking into account the advantages of the architecture of basic FPGAs and RSoCs. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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Features of TCAD and SPICE Simulation of a Charged Particle Impact into a 6T SRAM Cell Manufactured Using the CMOS 28-nm Technology Node

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russian microelectronics 2024年第7期53卷 737-743页

作者： Petrosyants, K.O. Silkin, D.S. Popov, D.A. Ismail-Zade, M.R. Kharitonov, I.A. Pereverzev, L.E. Morozov, A.A. Turgenev, P.V. National Research University Higher School of Economics Moscow Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia ООО AlphaCHIP Moscow Russia

Abstract—: With a decrease in the size of transistors, the conditions arise when the impact of one particle affects several transistors in the composition of a memory cell. Therefore, during simulation it is not sufficient to take into account one transistor directly hit by a particle. In this study, a full-size 3D model of two n-channel transistors that are part of a 6T memory cell in which the charged particle enters is considered. A particle impact simulation procedure is proposed that makes it possible to calculate the current pulse after the impact in a TCAD simulator and the response of memory cell circuit to an impact in a SPICE simulator using SPICE models. This procedure allows combining the advantages of the TCAD and SPICE calculations and achieve consistency between accuracy and the speed of simulation. The issues of determining the parameters of the TCAD model of a particle impact, the occurrence of a current pulse after a particle impact near a transistor in the on state, and the influence of the current of this transistor on the operation of a memory cell are considered. A technique of specifying the complex distribution profiles of charge carriers induced by particle impact in a TCAD simulator is proposed. Several cases of particle impact with different linear energy transfer (LET) values are simulated and an example of determining the critical LET value for a 6T SRAM cell with a design code of 28 nm is shown. The tailored parameters of the physical structure of the transistor make it possible to simulate the characteristics of transistors manufactured using the 28-nm CMOS technology node. © Pleiades Publishing, Ltd. 2024.

关键词： CMOS integrated circuits

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Room Response Equalizer Based on Simplified RLS Adaptive Filter 25

Room Response Equalizer Based on Simplified RLS Adaptive Fil...

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25th International Conference on Digital Signal Processing and its Applications, DSPA 2023

作者： Djigan, Victor Institute for Design Problems in Microelectronics of Russian Academy of Sicences Moscow Russia

ISBN: (纸本)9798350337235

An equalizer of a room acoustic frequency responses is presented in this paper. Such equalizers often require the usage of a large number of weights adaptive filter that means a large computational complexity of the filter and the equalizer. The considered equalizer uses the modified x-filtered Recursive Least Squares (RLS) adaptive filter. The computationally efficient fast RLS adaptive filters are often unstable if the number of their weights is large. That is why such filters are not suitable for the application in the room equalizers. The Matrix Inversion Lemma (MIL) RLS adaptive filters are stable but they are computationally complex in such applications. The equalizer presented in this paper uses a simplified MIL RLS adaptive filter. The correlation matrix of the filter is diagonalized. Besides, each of a square submatrix at the diagonal of the simplified correlation matrix are inverted using the computationally efficient version of the MIL which takes into consideration the symmetrical structure of these submatrices. The simulation proves the operability of the equalizer and demonstrates the efficiency of the simplified equalizer comparting to its full version. The demonstration includes different pictures like the frequency responses, power spectral densities and signal waveforms. © 2023 IEEE.

关键词： Equalizers

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CAD Architecture for Expansion of WSL-Based Combinational Circuits Dataset

CAD Architecture for Expansion of WSL-Based Combinational Ci...

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2024 International russian Smart Industry Conference, SmartIndustryCon 2024

作者： Zunin, V.V. Stempkovsky, A.L. Solovyev, R.A. Hse University Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9798350395044

The paper provides an overview of the current state of research in the field of combinational circuits reliability and parameters. Architecture of OpenLane flow, its components and main stages of work are described. Based on this flow, the main parameters are provided that will be used for augmentation and expansion of combinational circuits dataset and further testing. Previously developed software was elaborated to use OpenLane as its part. That is, now WSL (Ubuntu) can be used to launch OpenLane workflow from a Windows program without copying data from/to Linux system;subsequent parsing of the results to highlight the necessary parameters is implemented;parameters are saved to combinational circuits dataset. The modified software was tested for circuit generation and parameters calculation. © 2024 IEEE.

关键词： Timing circuits

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Development of Visualization Algorithms for Digital Integrated Circuits at the Gate Level

Development of Visualization Algorithms for Digital Integrat...

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2023 Seminar on Electrical Engineering, Automation and Control Systems: Theory and Practical Applications, EEACS 2023

作者： Goglev, Gorislav I. Tiunov, Ivan V. Russian Academy of Sciences Cad Department Institute for Design Problems in Microelectronics Moscow Russia

ISBN: (纸本)9798350358537

Graphical user interface is an inherent part of any modern computer aided design system, especially in micro- and nanoelectronics area. Carefully developed interface can notably simplify and boost up the integrated circuits design process. The proposed paper studies the problem of developing the placement and routing algorithms that are essential for solving the problem of digital integrated circuits visualization. These algorithms are the basis of a graphical design tool for digital circuits at the gate level. The suggested algorithms are built upon such known methods as ranking-based placement and Mikami-Tabuchi routing algorithm. In the paper, a graph model for a digital circuit representation and software implementation aspects are also proposed. The visualization results of some circuits from ISCAS'89 testbench are represented. © 2023 IEEE.

关键词： Visualization

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Segmentation of Prostate Cancer on TRUS Images Using ML

Segmentation of Prostate Cancer on TRUS Images Using ML

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2023 International russian Smart Industry Conference, SmartIndustryCon 2023

作者： Zaev, R.I. Romanov, A.Y. Solovyev, R.A. HSE University Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781665464291

Medical research has made tremendous progress in detecting various pathologies in the human body. There is still the problem of the speed of the process, and the lack of a sufficient number of trained professionals in this field. Detection of prostate cancer, in particular, without surgery is a very labor-intensive process. A neural network-based machine learning algorithm has been proposed to solve this problem, making it possible to see suspected areas of lesions in the organ. In this study, a comprehensive analysis of TRUS image processing approaches was carried out, and an algorithm architecture was developed to segment the affected areas. Based on this analysis, we have developed a system for automatic detection and segmentation of prostate cancer. © 2023 IEEE.

关键词： Diseases

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Automatic FPGA Placement Configuration for Customer designs

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russian microelectronics 2022年第7期51卷 579-584页

作者： Enns, V.I. Gavrilov, S.V. Chochaev, R. Zh. Research Institute of Molecular Electronics Moscow124460 Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124681 Russia

Abstract: Specialization of configurable heterogeneous ICs for specific customer proposals requires the flexibility of design and technological solutions. This, in turn, leads to the necessity of the automatic adjustment of CAD, including software placement tools, on the changes made. The development of efficient methods and tuning algorithms is impossible without relying on the appropriate mathematical apparatus. This study presents a set-theoretic mathematical model of a hierarchical project and formalizes a hierarchical approach to the netlist using the apparatus of set theory, mathematical logic, and graph theory. To ensure quick configuration of clustering and placement software tools, taking into account the changes made to the basic design, the correspondence between the elements of the basic FPGA design and user-designed circuits from the end user is formalized. The obtained results can serve as a base for the development of the efficient methods and algorithms for the automatic tuning of software clustering and placement tools. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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Pathfinder Algorithm Modification for FPGA Routing Stage

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russian microelectronics 2022年第7期51卷 573-578页

作者： Zapletina, M.A. Gavrilov, S.V. Institute for Design Problems in Microelectronics of the Russian Academy of Sciences Moscow Russia National Research University of Electronic Technology Moscow Russia

Abstract: One of the main advantages of FPGA design flow is the high development speed;therefore, the importance of effective computer-aided design tools for modern microcircuits of these classes cannot be overestimated. Placement and routing are the most time-consuming stages of FPGA design flow. The quality of results of these stages is crucial to the final performance of custom digital circuits implemented on FPGA. The paper discusses an approach to accelerating the routing stage within the layout synthesis flow for FPGA by introducing a few algorithmic improvements to a routing procedure. The basic routing algorithm under study is a modified Pathfinder for a mixed routing resources graph. Pathfinder is a well-known negotiation-based routing algorithm that works on the principle of iteratively eliminating congestions of chip routing resources. The sets of test digital circuits ISCAS’85, ISCAS’89, LGSynth’89 and several custom industrial projects were used for computational experiments. The impact of the proposed algorithmic improvements was analyzed using four FPGA architectures. It has been established that due to the improvements of the algorithm proposed in the paper, the average reduction in routing time was from 1.3 to 2.6 times, depending on the FPGA architecture, with no significant negative effect on the timing characteristics of the designed circuits. © 2022, Pleiades Publishing, Ltd.

关键词： Field programmable gate arrays (FPGA)

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