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Digital Signal Processing and its Applications (DSPA), International Conference on

作者： Victor Djigan Institute for Design Problems in Microelectronics of Russian Academy of Sicences Moscow Russia

An equalizer of a room acoustic frequency responses is presented in this paper. Such equalizers often require the usage of a large number of weights adaptive filter that means a large computational complexity of the filter and the equalizer. The considered equalizer uses the modified x-filtered Recursive Least Squares (RLS) adaptive filter. The computationally efficient fast RLS adaptive filters are often unstable if the number of their weights is large. That is why such filters are not suitable for the application in the room equalizers. The Matrix Inversion Lemma (MIL) RLS adaptive filters are stable but they are computationally complex in such applications. The equalizer presented in this paper uses a simplified MIL RLS adaptive filter. The correlation matrix of the filter is diagonalized. Besides, each of a square submatrix at the diagonal of the simplified correlation matrix are inverted using the computationally efficient version of the MIL which takes into consideration the symmetrical structure of these submatrices. The simulation proves the operability of the equalizer and demonstrates the efficiency of the simplified equalizer comparting to its full version. The demonstration includes different pictures like the frequency responses, power spectral densities and signal waveforms.

关键词： Symmetric matrices Correlation Equalizers Adaptive filters Signal processing algorithms Digital signal processing Filtering algorithms

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The Basics of Digital System designs Simulation for Hardware/Software Joint Debugging

The Basics of Digital System Designs Simulation for Hardware...

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2021 International Seminar on Electron Devices design and Production, SED 2021

作者： Ivannikov, Alexander Stempkovskiy, Alexander Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781665439411

Based on the analysis of the features of modern digital systems, the structure of a system for joint hardware/software simulation on functional-logic level are described. The purpose of the simulation is to debug a design of digital system before production. A hardware mathematical model is proposed, taking into account the peculiarities of modern digital systems, namely: The presence of bidirectional buses, high-impedance state of the outputs, internal memory of blocks. It is shown that the joint hardware/software simulation is reduced to solving systems of logical equations at each cycle of simulation. © 2021 IEEE.

关键词： Systems analysis

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Development of Visualization Algorithms for Digital Integrated Circuits at the Gate Level

Development of Visualization Algorithms for Digital Integrat...

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Electrical Engineering, Automation & Control Systems, Theory and Practical Applications (EEACS), Seminar on

作者： Gorislav I. Goglev Ivan V. Tiunov CAD Department Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow Russia

Graphical user interface is an inherent part of any modern computer aided design system, especially in micro- and nanoelectronics area. Carefully developed interface can notably simplify and boost up the integrated circuits design process. The proposed paper studies the problem of developing the placement and routing algorithms that are essential for solving the problem of digital integrated circuits visualization. These algorithms are the basis of a graphical design tool for digital circuits at the gate level. The suggested algorithms are built upon such known methods as ranking-based placement and Mikami-Tabuchi routing algorithm. In the paper, a graph model for a digital circuit representation and software implementation aspects are also proposed. The visualization results of some circuits from ISCAS'89 testbench are represented.

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Benchmarks and leaderboards for sound demixing tasks

arXiv

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arXiv 2023年

作者： Solovyev, Roman Stempkovskiy, Alexander Habruseva, Tatiana Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia Cork Ireland

Music demixing is the task of separating different tracks from the given single audio signal into components, such as drums, bass, and vocals from the rest of the accompaniment. Separation of sources is useful for a range of areas, including entertainment and hearing aids. In this paper, we introduce two new benchmarks for the sound source separation tasks and compare popular models for sound demixing, as well as their ensembles, on these benchmarks. For the models' assessments, we provide the leaderboard at https://***/quality_checker/, giving a comparison for a range of models. The new benchmark datasets are available for download. We also develop a novel approach for audio separation, based on the ensembling of different models that are suited best for the particular stem. The proposed solution was evaluated in the context of the Music Demixing Challenge 2023 and achieved top results in different tracks of the challenge. The code and the approach are open-sourced on GitHub. © 2023, CC BY-NC-SA.

关键词： Audition

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Radiation Hardened Components of Semicustom Analog Microcircuits

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russian microelectronics 2023年第7期52卷 599-607页

作者： Dvornikov, O.V. Tchekhovsky, V.A. Prokopenko, N.N. Galkin, Ya. D. Kunts, A.V. Chumakov, V.E. JSC Minsk Scientific Research Instrument-Making Institute Minsk220113 Belarus Belarusian State University Minsk220030 Belarus Don State Technical University Rostov Oblast Rostov-on-Don344002 Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Zelenograd124681 Russia Belarusian State University of Informatics and Radioelectronics Minsk220013 Belarus

Abstract—: An MH2XA031 master slice array (basic matrix crystal (BMC)) is applied for designing and semicustom production of analog integrated circuits (ICs) operating in extreme conditions. It can be effectively used only with a clear understanding of the permissible ranges of changes in the parameters of analog components when exposed to various types of penetrating radiation. In this study, with the help of circuit simulation, the effect of neutron fluence up to 1014 neutrons/cm2 and the absorbed dose of gamma rays up to 3 Mrad on the static parameters of the components of the MH2XA031 circuit design library—an ADComp3 comparator, an OAmp2 low zero offset voltage operational amplifier, an OAmp8 multidifferential operational amplifier, and a charge-sensitive amplifier (CSA) with an input double-gate transistor—is studied. It is established that the ADComp3 comparator, the OAmp2 and OAmp8 amplifiers, and the CSA remain operational at an absorbed dose of gamma rays equal to 3 Mrad. The permissible neutron fluence values for ADComp3, OAmp8, and CSA are 1014 neutrons/cm2;and for OAmp2, 1013 neutrons/cm2. It is established that modeling the radiation changes in the parameters of the components at higher neutron fluences (more than 1014 neutrons/cm2) and the absorbed gamma quanta of more than 3 Mrad is advisable after experimental verification of the adequacy of the transistor models used at the specified levels of penetrating radiation. © Pleiades Publishing, Ltd. 2023. ISSN 1063-7397, russian microelectronics, 2023, Vol. 52, No. 7, pp. 599–607. Pleiades Publishing, Ltd., 2023. russian Text The Author(s), 2022, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2022, Vol. 27, No. 3, pp. 308–321.

关键词： Operational amplifiers

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High-Speed Broadband Operational Amplifiers on a Master Slice Array

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russian microelectronics 2023年第7期52卷 702-710页

作者： Dvornikov, O.V. Tchekhovsky, V.A. Prokopenko, N.N. Galkin, Ya. D. Kunts, A.V. Chumakov, V.E. JSC Minsk Scientific Research Instrument-Making Institute Minsk220113 Belarus Belarusian State University Minsk220006 Belarus Don State Technical University Rostov oblast Rostov-on-Don344002 Russia Institute for Design Problems in Microelectronics Russian Academy of Sciences Moscow124365 Russia Belarusian State University of Informatics and Radioelectronics Minsk220013 Belarus

Abstract: High-speed operational amplifiers are widely used in quantum-optical systems and equipment for recording fast pulses. The high level of parameters of such products is ensured by the use of modern technological routes for manufacturing microcircuits containing complementary bipolar transistors with a high cutoff frequency and a low parasitic collector capacitance. These technological routes for the manufacture of microcircuits are not available in Russia and Belarus. In order to meet the existing needs of the domestic market for radio-electronic equipment, two operational amplifiers on an MN2KhA031 master slice array (MSA) with unified stages and the possibility of changing the parameters by selecting the resistance of the current-conducting resistors and the capacity of the balancing capacitor are presented. The circuit diagrams are described and the results of the circuit modeling of two products are presented: a high-speed operational amplifier OAmp9 with a gain bandwidth product of more than 600 MHz, an output voltage rise rate of over 400 V/μs with the static parameters corresponding to general-purpose operational amplifier applications, and a precision low-noise OAmp10 amplifier with a gain of about 2 × 106, an offset voltage of less than 50 μV, and a spectral noise floor relative to the input of about 1 nV/Hz0.5. The directions for further modernization of the developed amplifiers are formulated, especially, the reduction of the parasitic collector capacitance of transistors by design engineering, applying a reverse bias voltage, and the application of nonlinear correction circuits, which allow bringing the amplifiers’ performance in the large-signal mode closer to their performance in the low-signal mode. © Pleiades Publishing, Ltd. 2023. ISSN 1063-7397, russian microelectronics, 2023, Vol. 52, No. 7, pp. 702–710. Pleiades Publishing, Ltd., 2023. russian Text The Author(s), 2023, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Elektronika, 2023

关键词： Operational amplifiers

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Static Timing Analysis Method for Reconfigurable SoC with Various Types of Routing Resources

Static Timing Analysis Method for Reconfigurable SoC with Va...

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Electrical Engineering, Automation & Control Systems, Theory and Practical Applications (EEACS), Seminar on

作者： Vasilii M. Khvatov Computer Aided Design Department Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

Reconfigurable systems on a chip (RSoC) routing tree architecture consists of both digital elements and MOS switches. To evaluate the performance of routed integrated circuits (ICs), a netlist and a library of characterized elements is required. However, the MOS switch is an analog element and models for describing the time parameters of digital cells, including the non-linear delay model, cannot be applied to it. To solve this problem, this paper proposes a method for estimating the ICs performance based on the use of the connections equivalent electrical capacity and proposed formulas for calculating time parameters. The formulas were obtained as a result of researching the dependence of circuit timing characteristics on three parameters: the number of pass switches in the net, the load capacitance and the parameters of transistors at the output stage of the routing element. The approach allows to calculate the output signal parameters for various types of RSoC routing elements, including pass transistors, without critical losing of accuracy.

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Segmentation of Prostate Cancer on TRUS Images Using ML

Segmentation of Prostate Cancer on TRUS Images Using ML

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International russian Smart Industry Conference (SmartIndustryCon)

作者： R. I. Zaev A. Yu. Romanov R. A. Solovyev HSE University Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

Medical research has made tremendous progress in detecting various pathologies in the human body. There is still the problem of the speed of the process, and the lack of a sufficient number of trained professionals in this field. Detection of prostate cancer, in particular, without surgery is a very labor- intensive process. A neural network-based machine learning algorithm has been proposed to solve this problem, making it possible to see suspected areas of lesions in the organ. In this study, a comprehensive analysis of TRUS image processing approaches was carried out, and an algorithm architecture was developed to segment the affected areas. Based on this analysis, we have developed a system for automatic detection and segmentation of prostate cancer.

关键词： Measurement Industries Image segmentation Pathology Machine learning algorithms Neural networks Surgery

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Hardware Implementation of Convolutional Neural Network Based on Systolic Matrix Multiplier

Hardware Implementation of Convolutional Neural Network Base...

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Intelligent Technologies and Electronic Devices in Vehicle and Road Transport Complex (TIRVED)

作者： Alexander Stempkovskiy Roman Solovyev Dmitry Telpukhov Alexander Kustov Department of Design Methodology of Integrated Circuit Institute for Design Problems in Microelectronics of Russian Academy of Sciences (IPPM RAS) Moscow Russia

In this paper, we consider possibility of using matrix multipliers in hardware implementation of convolutional neural networks. Literature review has been conducted, existing matrix multiplication methods and their hardware implementations has been analyzed. Systolic algorithm for matrix multiplication (SMM) based on divide-and-conquer approach is proposed. This algorithm has been implemented as parameterized generator of hardware descriptions. Its positive and negative aspects are identified. Main difficulties of preparing feature maps for matrix multiplication are analyzed. Comparative analysis of hardware implementations of MobileNet neural network has been carried out for implementations based on convolutional blocks and implementations based on systolic matrix multiplier. A combined method is proposed that has the advantages of both approaches.

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Generation of Hardware Modules for Comparison in Residue Numeral Systems

Generation of Hardware Modules for Comparison in Residue Num...

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2021 International russian Automation Conference, RusAutoCon 2021

作者： Dergachev, S. Romanov, A. Solovyev, R. Hse University Moscow Russia Institute for Design Problems in Microelectronics of Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9780738131566

The residue numeral system (RNS) is one of the alternative number representation systems which has a strong potential for using it in computing systems. One of the known problems of the RNS is the complexity of the implementation of some basic arithmetic operations, including comparison and division operations. The paper considers the problem of implementing the comparator for the residue number system with one of the popular moduli set {2n-1, 2n, 2n+1}. Description of two existing methods and its properties are provided. After that, an experimental evaluation of the described methods using modern EDA tools and analysis of results are presented. © 2021 IEEE.

关键词： Comparators (optical)

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