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RScam: Cloud-based anti-malware via reversible sketch 11th

RScam: Cloud-based anti-malware via reversible sketch

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11th International Conference Security and Privacy in Communication Networks, SecureComm 2015

作者： Sun, Hao Wang, Xiaofeng Su, Jinshu Chen, Peixin College of Computer National University of Defense Technology Changsha China National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9783319288642

Cybercrime caused by malware becomes a persistent and damaging threat which makes the trusted security solution urgently demanded, especially for resource-constrained ends. The existing industry and academic approaches provide available anti-malware systems based on different perspectives. However, it is hard to achieve high performance detection and data privacy protection simultaneously. This paper proposes a cloud-based anti-malware system, called RScam, which provides fast and trusted security service for the resource-constrained ends. In RScam, we present suspicious bucket filtering, a novel signature-based detection mechanism based on the reversible sketch structure, which provides retrospective and accurate orientations of malicious signature fragments. Then we design a lightweight client which utilizes the digest of signature fragments to sharply reduce detection range. Finally, we design balanced interaction mechanism, which transmits sketch coordinates of suspicious file fragments and transformation of malicious signature fragments between the client and cloud server to protect data privacy and reduce traffic volume. We evaluate the performance of RScam with campus suspicious traffic and normal files. The results demonstrate validity and veracity of the proposed mechanism. Our system can outperform other existing systems with less time and traffic consumption. © Institute for Computer sciences, Social Informatics and Telecommunications Engineering 2015.

关键词： Malware

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DIPP——An LLC Replacement Policy for On-chip Dynamic Heterogeneous Multi-core Architecture

DIPP——An LLC Replacement Policy for On-chip Dynamic Hetero...

引用

International Conference of Young Computer Scientists, Engineers and Educators, ICYCSEE 2015

作者： Zhang Yang Xing Zuocheng Ma Xiao Science and technology on Parallel and distributed processing laboratory National University of Defense Technology

As the big data era is coming,it brings new challenges to the massive data processing.A combination of GPU and CPU on chip is the trend to release the pressure of large scale *** found that there are different memory access characteristics between GPU and *** most important one is that the programs of GPU include a large number of threads,which lead to higher access frequency in cache than the CPU *** the LRU policy favors the programs with high memory access frequency,the programs of GPU can't get the corresponding performance boost even more cache resources are *** LRU policy is not suitable for heterogeneous multi-core *** on the different characteristics of GPU and CPU programs on memory access,this paper proposes an LLC dynamic replacement policy--DIPP(Dynamic Insertion/Promotion Policy) for heterogeneous multi-core *** core idea of the replacement policy is to reduce the miss rate of the program and enhance the overall system performance by limiting the cache resources that GPU can acquire and reducing the thread interferences between *** compare the DIPP replacement policy with LRU and we conduct a classified discussion according to the program results of *** programs enhance 23.29% on the average performance(using arithmetic mean).Large working sets programs can improve 13.95%,compute-intensive programs enhance 9.66% and stream class programs improve 3.8%.

关键词： Big data Heterogeneous Multicore Replacement Policy DIPP

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Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture

Accelerating FDTD simulation of microwave pulse coupling int...

引用

IEEE Pacific Rim Conference on Communications, Computers and Signal processing, PACRIM 2015

作者： Wang, Qinglin Liu, Jie Cui, Xiantao Fu, Guitao Gong, Chunye Xing, Zuocheng Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China School of Computer Science National University of Defense Technology Changsha410073 China Beijing Satellite Navigation Center Beijing100094 China

ISBN: (纸本)9781467377881

The coupling of microwaves into apertures plays an important part in many electromagnetic physics and engineering fields. When the width of apertures is very small, Finite Difference Time Domain (FDTD) simulation of the coupling is very time-consuming. As a many-core architecture, the Intel's Many Integrated Core (MIC) architecture owns 512-bit vector units and more than 200 threads. In this paper, we parallelize FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture. In the implementation, the parallel programming model OpenMP is used to exploit thread parallelism while loop unrolling and SIMD intrinsic functions are utilized to accomplish vectorization. Compared with the serial version on Intel Xeon E5-2670 CPU, the implementation on the MIC coprocessor including 57 cores obtains a speedup of 11.57 times. The experiment results also demonstrate that the parallelization has good scalability in performance. Additionally, how binding relationship between OpenMP threads and hardware threads in MIC influences performance is also reported. © 2015 IEEE.

关键词： Scalability

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Unified virtual memory support for deep CNN accelerator on soC FPGA 1

引用

15th International Conference on Algorithms and Architectures for parallel processing, ICA3PP 2015

作者： Xiao, Tao Qiao, Yuran Shen, Junzhong Yang, Qianming Wen, Mei College of Computer National University of Defense Technology Changsha410073 China National Key Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha410073 China

ISBN: (数字)9783319271194

ISBN: (纸本)9783319271187

Cooperation of CPU and hardware accelerator on SoC FPGA to accomplish computational intensive tasks, provides significant advantages in performance and energy efficiency. However, current operating systems provide little support for accelerators: the OS is unaware that a computational task can be executed either on a CPU core or an accelerator, and provides no assistance in efficient management of data sharing between CPU and accelerator on the DRAM, such as zero copy, data coherence. It’s also hard for current OS to allocate large contiguous physical memory space for accelerator. In this paper, we select the Xilinx ZYNQ as target and qualitatively analyze methods of sharing data. Besides using high-performance (HP) AXI interfaces of the ZYQN device, we develop a novel memory management system for FPGA-based accelerator. It provides a unified virtual space for CPU cores and accelerator so that they can access the same memory space in the operating systems user space. For a deep convolutional neural network task, our design gains up to speed-up of 5. 34x compared to traditional processoraccelerator cooperation. © Springer International Publishing Switzerland 2015.

关键词： Energy efficiency

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Accelerating Monte Carlo Simulation of Neutron Transport on the Intel MIC Architecture

Accelerating Monte Carlo Simulation of Neutron Transport on ...

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International Conference on Information science and Control Engineering (ICISCE)

作者： Xiantao Cui Jie Liu Lihua Chi Qinglin Wang Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781467368513

Simulation of particle transport is critical for a great many of scientific and engineering domains. The Monte Carlo (MC) method is one of the most important numerical methods for the simulation of particle transport, and can simulate many complex types of particle transport. But the computation requirement of the MC simulation is very large. In 2010, Intel announced the Intel Many Integrated Core (MIC) architecture, which consists of many simple general-purpose cores and supports the well-known shared-memory execution model that is the base of most nodes in HPC machines. On account of the independence of simulation of each particle in the MC method, it is well-suited to accelerate the MC simulation on MIC. In this paper, an algorithm named MCNP-MIC based MIC is presented for MC simulation of neutron transport in the context of deep penetration problem, which includes the development of parallel random generator, the assignment of particle number based thread number and the design of high efficiency data structures for parallelism. Eventually, we get the results as follows: with the same problem scale and computational accuracy, the MCNPMIC algorithm has achieved roughly 5.6-fold speedup running on a 57-core MIC chip in comparison with the serial MCNP algorithm on an Intel Xeon E5-2670 CPU.

关键词： Microwave integrated circuits Neutrons Algorithm design and analysis Monte Carlo methods Data structures Graphics processing units

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Pallas: An Application-Driven Task and Network Simulation Framework

Pallas: An Application-Driven Task and Network Simulation Fr...

引用

IEEE International Conference on Cluster Computing

作者： Yuming Ye Ziyang Li Dongsheng Li Yiming Zhang Feng Liu Yuxing Peng National Laboratory for Parallel and Distributed Processing National University of Defense Technology

ISBN: (纸本)9781467365994

With the help of simulation tools, users can evaluate new proposals in cluster environment efficiently. However, current cloud simulators cannot meet the needs of application-driven simulation scenarios. In this paper, we propose Pallas, a task and network simulation framework that supports various cloud applications. Task-aware network scheduling and network-perceived task placement algorithms can be easily implemented in Pallas. We present the architecture and main components of Pallas and evaluate its effectiveness by comparing algorithm improvements to the actual results.

关键词： Computational modeling Semantics Scheduling algorithms Clustering algorithms Yttrium Computer architecture

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RaceChecker: Efficient Identification of Harmful Data Races

RaceChecker: Efficient Identification of Harmful Data Races

引用

Euromicro Conference on parallel, distributed and Network-Based processing

作者： Kai Lu Zhendong Wu Xiaoping Wang Chen Chen Xu Zhou Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha PR China

ISBN: (纸本)9781479984923

Data races hidden in concurrent programs have caused severe failures. To improve the reliability, many race detectors are proposed. However, most of the reported races are not harmful, which consumes manual effort to identify the harmful races. This paper proposes RaceChecker that can detect the potential races and identify the harmful races effectively and efficiently. Unlike previous detectors, RaceChecker combines happens-before relation and ad-hoc synchronization to prune the infeasible races so that fewer potential races are required to be verified. Before verification, RaceChecker groups the remaining potential races, guaranteeing the potential races in one group do not interfere with each other. Therefore, multiple potential races in one group can be verified together in one execution. To our knowledge, this is the first effective technique that groups the potential races to improve the efficiency. Unlike previous detectors that verify one potential race in one execution, RaceChecker dynamically controls thread scheduler to create real race conditions to verify multiple potential races in one execution, identifying the harmful races that cause program failures. We have implemented RaceChecker as a prototype tool and have experimented on a number of real-world concurrent programs. Results show that 66% of the potential races are infeasible and nearly 48% of the executions are reduced by the grouping strategy. The known harmful races are also identified effectively. By pruning and grouping, RaceChecker identifies the harmful races more efficiently. Comparing with RaceMob and RaceFuzzer, the time is reduced significantly, with an average of 45% and 81% respectively.

关键词： Detectors Synchronization Concurrent computing Programming Relays Instruction sets Monitoring

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Partial Clones for Stragglers in MapReduce

Partial Clones for Stragglers in MapReduce

引用

International Conference of Young Computer Scientists, Engineers and Educators, ICYCSEE 2015

作者： Jia Li Changjian Wang Dongsheng Li Zhen Huang National Laboratory for Parallel and Distributed Processing School of Computer ScienceNational University of Defense Technology

Stragglers can temporize jobs and reduce cluster efficiency *** researches have been contributed to the solution,such as Blacklist[8],speculative execution[1,6],Dolly[8].In this paper,we put forward a new approach for mitigating stragglers in Map Reduce,name *** starts task clones only for high-risk delaying *** experiments have been carried and results show that it can decrease the job delaying risk with fewer resources *** small jobs,Hummer also improves job completion time by 48% and 10% compared to LATE and Dolly.

关键词： MapReduce mitigating stragglers task clones

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Area-efficient High-throughput Sorted QR Decomposition-based MIMO Detector on FPGA

Area-efficient High-throughput Sorted QR Decomposition-based...

引用

2015 IEEE International Conference on Computer and Communications(ICCC 2015)

作者： Tong Zhou Song Guo Yuanwu Lei Yong Dou National Laboratory for Parallel and Distributed Processing National University of Defense Technology

This paper aimed to improve MIMO detector's performance in both throughput and cost. Thus, it presents a FPGA architecture implementation for the SQRD detection in a 4′4 16-QAM MIMO wireless communication systems. The exploitation of fine-grained parallelism and coarse-grained parallelism strategies are responsible for bettering the performance of the implementation. Besides, this paper proposes a method to ensure the correctness of the implementation of time-sharing modules, which is general and applicable to any MIMO detector implementation. The work results in a real-time FPGA-based implementation delivering 32 MSQRD/s with 5.2 us latency and lowering more than 50\% cost in hardware resources on a Xilinx Virtex6.

关键词： SQRD parallel architecture time-sharing FPGA

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Pillow talks: Bits over communications in WLAN 2

Pillow talks: Bits over communications in WLAN

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2nd Workshop for Mobile Sensing, Computing and Communication, MSCC 2015

作者： Dong, Xuan Zhu, Chunsheng Lv, Shaohe Wang, Lei Wang, Xiaodong Leung, Victor C.M. National Laboratory of Parallel and Distributed Processing National University of Defense Technology United States Department of Electrical and Computer Engineering University of British Columbia Canada Department of Network Engineering Dalian University of Technology China

ISBN: (纸本)9781450335188

Improving the channel utilization is a significant issue to enhance the performance in WLAN. This paper presents, Pillow Talks MAC (PT-MAC), a novel spectrum sharing mechanism to create an extra channel (pt-channel) for client- to-client transmission in WLAN. Obviously, The basic chal- lenge in our proposal is how pt-channel works concurrently and transparently with AP transmissions. To address the issue, in PT-MAC, selected clients are allowed to contend for pt-channel during uplink transmissions and talk freely under the ongoing downlink transmissions. Based on ad- vanced physical techniques, pt-channel transmitter receives and forwards the AP signals simultaneously within OFDM cyclic prefix, resulting in mixed signals are overheard by re- ceiver in pt-channel. However, the mixed message can be re- covered by pt-decoding system. Simulations and analytical results show that, PT-MAC reuses the spectrum in WLAN and achieves a throughput gain as large as 92% with similar fairness, when the ratio of downlink traffic is about 80%. © 2015 ACM.

关键词： Wireless local area networks (WLAN)

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