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作者： Li, Zongzhe Lu, Yao Cao, Wei Wang, Yongxian Wang, Zhenghua Parallel and Distributed Processing for National Laboratory School of Computer Science National University of Defence Lechnology Changsha Hunan 410073 China

ISBN: (纸本)9781424472369

In this paper, we explore a parallel block multigrid preconditioner based on factorization of the coefficient matrix generated in three-dimensional unstructured grids system. This preconditioner is robust with respect to the magnitude of the mesh size and the coefficient complexity, apply smoothed aggregation algebraic multigrid which using block lower-upper symmetric Gauss-Seidel(BLU-SGS) as smoother to accelerate convergent rate. We focus on this method to three-dimensional, unstructured, large-scale, parallel and NS equations' steady-state simulations. The numerical results which conducted on NACA0012 airfoil indicate that nearly optimal convergence rates and computational complexity for parallel solutions, this method also provide high speedup and efficiency for a series of processors. © 2010 IEEE.

关键词： Navier Stokes equations

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A load balancing-supported constant degree DHT ID assignment method

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Tien Tzu Hsueh Pao/Acta Electronica Sinica 2010年第11期38卷 2649-2654页

作者： Wang, Xiao-Hai Peng, Yu-Xing Li, Dong-Sheng Key Laboratory of Science and Technology for Parallel and Distributed Processing National University of Defense Technology Changsha Hunan 410073 China

A Load Balancing-Supported ID assignment method is the foundation to implement and maintain DHT overlays, realized constant degree DHTs usually use simple pure centralized or distributed ID management strategies, which cannot resolve the contradiction between cost of maintaining topologies' information and topologies' balance. Analyzing the universal tree structures in the topologies, an ID Assignment method RFIDAM based on the internal structure Routing Forest is proposed, which regularly aggregates local balancing information to guide new nodes' joining for overall balance. The experimental results show, with low maintenance and routing message overhead, the system's loading balance is efficiently ensured with the length of IDs differ by at most 2.

关键词： Topology

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High performance and memory efficient implementation of matrix multiplication on FPGAs

High performance and memory efficient implementation of matr...

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2010 International Conference on Field-Programmable technology, FPT'10

作者： Wu, Guiming Dou, Yong Wang, Miao National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China Jiangnan Institute of Computing Technology Wuxi 214083 China

ISBN: (纸本)9781424489817

We present a high performance and memory efficient hardware implementation of matrix multiplication for dense matrices of any size on the FPGA devices. By applying a series of transformations and optimizations on the original serial algorithm, we can obtain an I/O and memory optimized block algorithm for matrix multiplication on FPGAs. A linear array of processing elements (PEs) is proposed to implement this block algorithm. We show significant reduction in hardware resources consuming compared to the related work while increasing clock frequency. Moreover, the memory requirement can be reduced to O(S) from O(S 2), where S is the block size. Therefore, more PEs can be integrated into the same FPGA devices. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Automatic synthesis of processor arrays with local memories on FPGAs

Automatic synthesis of processor arrays with local memories ...

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2010 International Conference on Field-Programmable technology, FPT'10

ISBN: (纸本)9781424489817

In this paper, we present an automatic synthesis framework to map loop nests to processor arrays with local memories on FPGAs. An affine transformation approach is firstly proposed to address space-time mapping problem. Then a data-driven architecture model is introduced to enable automatic generation of processor arrays by extracting this data-driven architecture model from transformed loop nests. Some techniques including memory allocation, communication generation and control generation are presented. Synthesizable RTL codes can be easily generated from the architecture model built by these techniques. A preliminary synthesis tool is implemented based on PLUTO, an automatic polyhedral source-to-source transformation and parallelization framework. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Routing with uncertainty in wireless mesh networks

Routing with uncertainty in wireless mesh networks

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2010 IEEE 18th International Workshop on Quality of Service, IWQoS 2010

作者： Chen, Fajun Liu, Jiangchuan Li, Zongpeng Wang, Yijie Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing School of Computer National University of Defense Technology China School of Computing Science Simon Fraser University Canada Department of Computer Science University of Caglary Canada

ISBN: (纸本)9781424459889

Existing routing protocols for Wireless Mesh Networks (WMNs) are generally optimized with statistical link measures, while not addressing on the intrinsic uncertainty of wireless links. We show evidence that, with the transient link uncertainties at PHY and MAC layers, a pseudo-deterministic routing protocol that relies on average or historic statistics can hardly explore the full potentials of a multi-hop wireless mesh. We study optimal WMN routing using probing-based online anypath forwarding, with explicit consideration of transient link uncertainties. We show the underlying connection between WMN routing and the classic Canadian Traveller Problem (CTP) [1]. Inspired by a stochastic recoverable version of CTP (SRCTP), we develop a practical SRCTP-based online routing algorithm under link uncertainties. We study how dynamic next hop selection can be done with low cost, and derive a systematic selection order for minimizing transmission delay. We conduct simulation studies to verify the effectiveness of the SRCTP algorithms under diverse network configurations. In particular, compared to deterministic routing, reduction of end-to-end delay (51:15∼73:02%) and improvement on packet delivery ratio (99:76%) are observed.

关键词： Routing protocols

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Window memory accesses method in alternate row/column matrix access systems

Window memory accesses method in alternate row/column matrix...

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2010 2nd International Conference on Computer Engineering and technology, ICCET 2010

作者： Jie, Zhou Dou, Yong Lei, Yuanwu Dong, Yazhuo National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China Unit 91655 People's Republic of China Beijing China

ISBN: (纸本)9781424463503

Many systems, such as Synthetic Aperture Radar (SAR) processing, two-dimensional image processing, 2d-FFT calculation, need access the row and column data of their matrix alternately. The DRAM memory should be used due to huge data in these systems. To improve the usage of memory bandwidth in such systems, this paper theoretically analyses the optimal window size to minimize the total number of opening/closing pages when performing in such instances by balancing the number of handling physical pages between row and column accesses. This paper presents a window-based optimal memory access method, and we implemented an FPGA-based SDRAM controller with eight simple ports, which is based on window accessing mechanism and supports commercialized SDARM. The experimental results show that the effective I/O bandwidth of external SDRAM using our window layout approach increases from 114.2MB/s of naive implementation to 730.2MB/s with over 6X speedup. In addition, we implemented two SAR processing systems with four FFT processing elements using our window-based SDRAM controller and Corner Turn method separately in FPGA chip. Results show window-based method can achieve a speedup of 2.6 compared to Corner Turn method. © 2010 IEEE.

关键词： Fast Fourier transforms

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Simulation research of communication networks based on prim algorithm

Simulation research of communication networks based on prim ...

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International Forum on Information technology and Applications

作者： Yang, Chenghui Ren, ChuanJun College of Electrical Engineering Northwest University for Nationalities Lanzhou 730030 China National Laboratory for Parallel and Distributed Processing College of Computer Science National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769541150

In order to improve the efficiency of the communication networks, we used the Kruskal algorithm and the Prim algorithm through algorithm comparison and analysis methods of data structure. A dynamic framework for the communication network installed system is built. Moreover, according to the actual framework of the communication network specific issues, the module chooses the Minimum Cost Spanning Tree Prim algorithm ultimately. The assumptions process and outcomes simulation have proper analysis and certification by C language. Experimental results show that the Minimum Cost Spanning Tree of Prim algorithm on the installed system for communication networks dynamic planning process have the advantage of speed and effectively reduce the waste of resources, which not only can ensure efficiency but also can effectively improve communication networks installed cost. © 2010 IEEE.

关键词： Costs

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A high efficient in-place transposition scheme for multidimensional arrays

A high efficient in-place transposition scheme for multidime...

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3rd International Conference on Information and Computing, ICIC 2010

作者： Yuan, Jie Wu, Jian-Ping Wang, Zheng-Hua National Lab. of Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer Science National University of Defense Changsha China

ISBN: (纸本)9780769540474

This paper presents a in-place cycle-reducing method for multidimensional arrays transposition in local memory to reduce the memory R/W operations. The resulting method can significantly reduce the number of subcycles (also called following-cycles) and that of memory operations for square arrays. Taking square array 256 by 256 for example, the number of subcycles used by current available best algorithm can be reduced from 32894 to only 574, using our new method, and the memory operation number can be reduced by about 32.58%, from 98430 to 66366. Taking advantage of this new method, the elapsed time can be reduced as a result. The number of cycles and operations can also be reduced for 2D rectangle arrays with 2m rows and 2n column stored in column-major, especially n=2m, even though the improvement is not as significant as that for square arrays. The improved 2D in-place algorithm has been extended to 3D arrays, and some theoretic and numerical results are also provided. Furthermore, we develop a new in-place 3D arrays transposition algorithm. This algorithm is very important for a deep research for multidimensional arrays. Experimental results show that our algorithm can improve efficiency significantly, compared to some other 3D array transposition schemes. © 2010 IEEE.

关键词： Multidimensional array Memory operation Cycle-reducing Transposition In-place transposition Transposition arrays three-dimensional array Local Memory MULTIDIMENSIONAL

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parallel transposing and communication strategies for FFT on cluster of SMP architectures with multicore processors

Parallel transposing and communication strategies for FFT on...

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Congress on Image and Signal processing, CISP

ISBN: (纸本)9781424465149

This paper presents a high performance parallel formulation for 1-D FFT based on transpose algorithm. The parallel scheme of FFT trades off some efficiency for a more consistent level of parallel performance. It involves matrix transposition, and a new in-place transposing algorithm is introduced into the parallel matrix transposition to improve the efficiency. Depending on the size of the input n, the number of processes p, and the memory or network bandwidth, this method can achieve better parallel performance than the other on cluster of SMP architectures. Test shows us that our scheme can achieve a good speedup. ©2010 IEEE.

关键词： Fast Fourier transforms

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A simulated annealing technique for optimizing timewarp simulation

A simulated annealing technique for optimizing timewarp simu...

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2010 International Conference on Computer Modeling and Simulation, ICCMS 2010

作者： Zhang, Wei Meraji, Sina Wang, Jun Tropper, Carl National Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha 410073 China School of Computer Science McGill University Montreal H3A 2A7 Canada

ISBN: (纸本)9780769539416

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of Time Warp simulations. © 2010 IEEE.

关键词： Simulated annealing

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