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检索条件"机构=The Science and Technology on Parallel and Distributed Processing Laboratory"

共 1124 条记录，以下是971-980 订阅

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Exploiting Fine-Grained Pipeline parallelism for Wavefront Computations on Multicore Platforms

Exploiting Fine-Grained Pipeline Parallelism for Wavefront C...

引用

International Conference on parallel processing Workshops (ICPPW)

作者： Guiming Wu Miao Wang Yong Dou Fei Xia National Laboratory for Parallel & Distributed Processing National University of Defense Technology Changsha China

This paper presents our experience with exploiting fine-grained pipeline parallelism for wavefront computations on a multicore platform. Wavefront computations have been widely applied in many application areas such as scientific computing algorithms and dynamic programming algorithms. To exploit fine-grained parallelism on multicore platforms, the programmers must consider the problems of synchronization, scheduling strategies and data locality. This paper shows the impact of fine-grained synchronization methods, scheduling strategies and data tile sizes on performance. We propose a low cost, lock-free, and lightweight synchronization method that can fully exploit pipeline parallelism. Our evaluation shows that RNAfold, an application for RNA secondary structures prediction, can achieve the best speedup of 3.88 on four cores under our framework.

关键词： Pipelines parallel processing Concurrent computing Multicore processing Heuristic algorithms Processor scheduling Scientific computing Dynamic programming Programming profession Tiles

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A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs

A Fine-grained Pipelined Implementation of the LINPACK Bench...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Guiming Wu Yong Dou Yuanwu Lei Jie Zhou Miao Wang Jingfei Jiang National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China

Previous works have projected that the peak performance of FPGAs can outperform that of the general purpose processors. However, no work actually compares the performance between FPGAs and CPUs using the standard benchmarks such as the LINPACK benchmark. We propose and implement an FPGA-based hardware design of the LINPACK benchmark, the key step of which is LU decomposition with pivoting. We introduce a fine-grained pipelined LU decomposition algorithm that enables optimum performance by exploiting fine-grained pipeline parallelism. A scalable linear array of processing elements (PEs), which is the core component of our hardware design, is proposed to implement this algorithm. To the best of our knowledge, this is the first reported FPGA-based pipelined implementation of LU decomposition with pivoting. A total of 19 PEs can be integrated into an Altera Stratix II EP2S130F1020C5 on our self-designed development board. Experimental results show that the speedup up to 6.14 can be achieved relative to a Pentium 4 processor for the LINPACK benchmark.

关键词： Field programmable gate arrays Hardware Equations Algorithm design and analysis Concurrent computing distributed computing Laboratories distributed processing Pipelines parallel processing

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A Peer-to-Peer Media Streaming System Based on the iVCE Platform

A Peer-to-Peer Media Streaming System Based on the iVCE Plat...

引用

International Conference on parallel and distributed Systems (ICPADS)

作者： Jiqing Wu Yuxing Peng Rui Shen National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

With the advancement of peer-to-peer technology, media streaming applications become more and more popular in the Internet. However, the traditional development methods for this kind of applications need developers not only to consider the application logic but also to manage the dynamics of Internet resources, thus increasing the difficulty of development and limiting the deployment of personal video distribution applications. In this paper, we design and implement a peer-to-peer streaming system in a much easier way. In this way we can concentrate on the application itself without distraction from the dynamics of Internet resources. Such simplification owes to the Internet-based Virtual Computing Environment (iVCE), which provides programming abstractions and runtime utilities that can encapsulate the complexity of managing transient resources into the platform, thus facilitating the construction of Internet applications. When we build our streaming application based on the iVCE, we only need to define the interaction protocols among distributed nodes with the Owlet programming language. Also, we implement a JavaBean, which can be used by the Owlet program, to assist the transferring and rendering of the content. Our implementation shows that peer-to-peer applications such as media streaming, can be elegantly built using the iVCE platform, and it can serve as a reference implementation for developing similar applications.

关键词： Streaming media Peer to peer computing Internet Resource management Logic Utility programs Runtime environment Environmental management Protocols Computer languages

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Optimization techniques of on-chip memory system based on UltraSPARC architecture

Optimization techniques of on-chip memory system based on Ul...

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Anwen Huang Jun Gao Chaochao Feng Minxuan Zhang Key Laboratory of Science and Technology of National Defense of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China

It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary element of on-chip memory system is simulated by ModelSim and synthesized by Synopsys Design Complier with 90 nm standard cell library. Aimed at the potential limiting factor of improving the performance of memory hierarchy, corresponding optimization techniques of critical elements in memory system are explored finally.

关键词： System-on-a-chip Elliptic curve cryptography Hardware Costs Algorithm design and analysis Random access memory Clocks Registers Elliptic curves Protection

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Matrix Inversion on the Cell/B.E. Processor

Matrix Inversion on the Cell/B.E. Processor

引用

IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Shodai Yokoyama Kazuya Matsumoto Stanislav Sedukhin Distributed Parallel Processing Laboratory Graduate School of Computer Science and Engineering University of Aizu Japan

The problem of inverting matrices is one that occurs in some problems of practical importance. This paper introduces and evaluates the block algorithm for high performance matrix inversion on the Cell Broadband Engine (Cell/B.E.) processor. The Cell/B.E. is a heterogeneous multi-core processor on a single-chip jointly developed by Sony, Toshiba and IBM, which has a very high speed of the single precision floating-point arithmetic. The discussed matrix inversion algorithm is a combination of the block algebraic path problem algorithm and the well-known block matrix inversion algorithm based on the LU decomposition. For relatively big matrices, this combined block algorithm spends the most time in computing matrix-matrix multiplication of blocks and achieves 149.4 Gflop/s on Cell/B.E., when PPE and six SPEs of PlayStation3 are used, or 93.4% of the aggregated double (PPE) and single (SPEs) precision peak performance, which is 160.0 Gflop/s.

关键词： Matrix decomposition Partitioning algorithms Floating-point arithmetic Engines Multicore processing Microprocessors Reduced instruction set computing High performance computing parallel processing Computer science

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A Two-Phase Mapping Method for parallel Applications Simulation

A Two-Phase Mapping Method for Parallel Applications Simulat...

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International Conference on Computational Intelligence and Software Engineering (CiSE)

作者： Jianbin Fang Chuanfu Xu Yonggang Che Yufen Weng Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Efficient mapping of logical processes to physical processes is one of key technologies to accelerate parallel performance simulation. Aiming at minimizing the communications between SMP nodes and between host physical processes, this paper presents a novel method named TPsmp-LP 3 M. It automatically extracts communication pattern of logical processes from trace and then generates a two-phase mapping from logical processes to SMP clusters. Experimental results show that TPsmp-LP 3 M can outperform the regular mapping method by up to 20.2%.

关键词： Computational modeling Computer simulation Bandwidth Predictive models Discrete event simulation Concurrent computing parallel processing Application software Laboratories distributed processing

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iRank: Supporting Proximity Ranking for Peer-to-Peer Applications

iRank: Supporting Proximity Ranking for Peer-to-Peer Applica...

引用

International Conference on parallel and distributed Systems (ICPADS)

作者： Yongquan Fu Yijie Wang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology China

Proximity ranking according to end-to-end network distances (e.g., Round-Trip Time, RTT) can reveal detailed proximity information, which is important in network management and performance diagnosis in distributed systems. However, to the best of our knowledge, there has been no similar work on this subject in the P2P computing field. We present a distributed rating method iRank, that enables proximity rankings by providing discrete ratings in a distributed manner. It formulates the proximity ranking as a rating problem that faithfully captures the proximity based on noisy distance measurements scalably and practically. The primary challenge in inferring proximity rankings is enforcing distributed ratings with complex rating policies. Our solution is based on reconstructing ratings by decomposing a centralized rating method Maximum Margin Matrix Factorization (MMMF) into independent sub-problems, that can be efficiently solved in a decentralized manner. By relaxing the dependence on infrastructure nodes that are a single point of failure and limit scalability, iRank can gracefully handle network churns. Through real network latency data sets, we demonstrate that iRank can predict ratings with low distortion, which are smaller than 20 percentage worse than the centralized method, in the context of synthetic complex rating policies.

关键词： Peer to peer computing distributed computing Computer networks Network servers Application software Laboratories distributed processing Concurrent computing Computer network management Conference management

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Towards efficient mapping in large-scale trace-driven parallel performance simulation

Towards efficient mapping in large-scale trace-driven parall...

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IEEE Youth Conference on Information, Computing and Telecommunication, YC-ICT

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

In parallel performance simulation of parallel systems, a large amount of logic processes (LP) must be mapped to relatively small number of physical elements (PE). Previous researches have shown that different mapping schemes could result in significant variation in the whole parallel simulation cost. In this paper, we propose, implement, and evaluate a minimum communication-guided mapping (MiniCoM) scheme for large-scale trace-driven parallel performance simulation. Guided by extracted information about interactions among LPs from previously generated traces, MiniCoM can map some most frequently interacted LPs to the same PE while trying to keep load balance between PEs. The mapping aims to minimize realistic communications among PEs which may run on different nodes of host systems with large inter-node latency. We use BigSim simulator and two target programs to evaluate MiniCoM. Our results show that MiniCoM is more efficient than blocked mapping adopted by BigSim: it can reduce the total parallel simulation runtime by up to 49%.

关键词： Large-scale systems Computational modeling parallel processing Discrete event simulation Computer simulation Concurrent computing Data mining Laboratories distributed processing distributed computing

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A Virtual Machine Server Aggregation Algorithm Based on Hierarchical Clustering

A Virtual Machine Server Aggregation Algorithm Based on Hier...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Feng Huang Dongsheng Li National Laboratory of Parallel and Distributed Processing College of Computer National University of Defense Technology Changsha China

Combining virtual machine technology and network computing technology will be able to effectively aggregate the widely distributed heterogeneous and autonomous resources in the Internet. This paper proposes a virtual machine server aggregation algorithm, called DVSA, based on hierarchical clustering method for virtual computing environment. According to network latencies, the algorithm clusters virtual machine servers into groups. If servers in the same group are scheduled, the latencies between virtual machines which host on these servers will be small, and the performance and stability of the distributed execution environment could be improved.

关键词： Virtual machining Clustering algorithms Network servers Web server Delay Computers Aggregates IP networks Clustering methods Processor scheduling

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Simulation and analysis of single-electron transistors with 1-dimension multiple islands

Simulation and analysis of single-electron transistors with ...

引用

IEEE Conference on Nanotechnology

作者： Bingcai Sui Yaqing Chi Hailiang Zhou Chao Zhang Liang Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

ISBN: (纸本)9781424448326

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. Based on the Monte Carlo (MC) and stable diagram method, the critical problems during simulating and analyzing the SETs with multi-islands are investigated, e.g. capacitance matrix, potential of the islands, the free energy and so on. Meanwhile, double-island SET is simulated and analyzed as an example of SETs with 1-D muti-islands in detail. For the first time, 3-D stable diagram is obtained, and some new phenomena are analyzed in the paper. And through analyzing the result it's shown that although SETs with 1-D muti-islands is more useful and powerful than SETs with single island, there inevitably exists many effects because of the coupling energy between the islands.

关键词： Analytical models Single electron transistors Tunneling Carbon nanotubes Capacitance Voltage Energy consumption Capacitors Very large scale integration Temperature

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