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检索条件"机构=Video Technology Research Group Graduate Program in Computing"

共 86 条记录，以下是11-20 订阅

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Neural Network Based Light Field Predictors: An Evaluation

Neural Network Based Light Field Predictors: An Evaluation

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Matheus Jahnke Ítalo D. Machado Lucas Ikenoue Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

Processing and storing the 4D structure of light fields can be challenging and expensive due to the high-dimensional data and its unique characteristics. There are plenty of works employing convolutional neural networks (CNNs) for light field prediction and encoding. Nonetheless, to the best of our knowledge, the literature lacks an efficiency evaluation of different CNN architectures as well as 4D neural networks for these purposes. Therefore, this paper presents an experimental study that assesses the performance of pipeline and U-net convolutional neural networks for light field block prediction in both spatial and angular dimensions. Additionally, we compare these architectures with a novel 4D network that aims to exploit the light field data structure. The results of the study show that U-net and 4D networks outperform classical CNN architectures in terms of prediction accuracy and residue generation. Furthermore, the spatial dimension prediction provides more valuable information for the networks to learn, improving their prediction by 5dB.

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Multi-Codec video Quality Enhancement Model Based on Spatio- Temporal Deformable Fusion

Multi-Codec Video Quality Enhancement Model Based on Spatio-...

引用

IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Gilberto Kreisler Garibaldi Da Silveira Bruno Zatt Daniel Palomino Guilherme Corrêa Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

The popularization of mobile phones and other multimedia portable devices paved the way for the increase in video consumption worldwide. However, it is impossible to transmit a non-compressed video due to the high bandwidth required. To achieve significant compression rates, video codecs usually employ methods that damage the visual quality perceived by the end user in non-negligible levels. Different architectures based on deep learning have been recently proposed for video Quality Enhancement (VQE). Still, most of them are trained and validated using videos generated by a single codec under fixed configurations. With the increase of video coding formats and standards on the market, VQE methods that apply to different contexts are desired. This paper proposes a new VQE model based on the Spatio- Temporal Deformable Fusion (STDF) archi-tecture, providing quality gains for videos compressed according to different formats and standards, such as HEVC, VVC, VP9, and AVI. The results demonstrate that by considering different video coding standards and formats to build the STDF model, a significant increase in VQE is achieved, with an average PSNR increment of up to 0.382 dB.

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An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow

An UHD 4K@120fps Hardware for the VVC Prediction Refinement ...

引用

Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Murilo Perleberg Marcello M. Muñoz Denis Maass Vladimir Afonso Luciano Agostini Marcelo Porto Video Technology Research Group Graduate Program in Computing Federal University of Pelotas Pelotas Brazil Video Technology Research Group Sul-rio-grandense Federal Institute Pelotas Brazil

This work presents a hardware design for the Prediction Refinement with Optical Flow (PROF). The PROF is incorporated in the Affine Prediction from the recent Versatile video Coding (VVC) standard. While the Affine Prediction allows the representation of complex motions in the scene as rotation, zoom, and skew, by performing motion compensation over each subblock of the current block, the PROF enhances video encoding efficiency by generating the virtual rotation of each subblock. However, the PROF supports a wide range of block sizes, demanding intensive computational processing and therefore requiring dedicated hardware design. So, the PROF Hardware Design was developed to process one 4×4 subblock at each clock cycle. The synthesis results for TSMC 40nm technology show that the PROF Hardware Design can process 120 frames per second of Ultra-High Definition UHD 4K resolution videos while dissipating 0.98mW when operating at 62MHz. This work also presents integration between the PROF Hardware Design and an Affine Motion Compensation hardware. To the best of author's knowledge, this is the first hardware design for PROF processing in the literature.

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H.264-to-AV1 video Transcoding Acceleration Based on Lightweight Machine Learning

H.264-to-AV1 Video Transcoding Acceleration Based on Lightwe...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Alex Borges Marcelo Porto Bruno Zatt Guilherme Correa Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

video streaming platforms have been using the H.264/AVC standard for a long time, even though it was released almost 20 years ago and much more efficient codecs are currently available. The AOMedia video 1 (AV1) format is an alternative with significant coding efficiency gains in comparison to H.264/AVC, besides being a royalty-free format. However, migrating legacy content from older to newer formats is a costly task, which requires long processing times. This work presents a solution for accelerating the H.264-to-AV1 transcoder based on machine learning. Sixteen decision tree models trained with data gathered during the H.264/AVC decoding and the AV1 encoding processes are proposed and implemented in the libaom reference software, leading to a complexity reduction of 18.96% at the cost of coding efficiency losses of 2.85% on average. To the best of the authors' knowledge, this is the first H.264-to-AV1 transcoding acceleration solution published in the literature.

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Using Decision Trees to Accelerate the H.266/VVC-to-AV1 video Transcoding

Using Decision Trees to Accelerate the H.266/VVC-to-AV1 Vide...

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Brazilian Symposium on Computer Graphics and Image Processing (SIBGRAPI)

作者： Caroline Camargo Alex Borges Bruno Zatt Marcelo Porto Guilherme Correa Video Technology Research Group - ViTech Graduate Program in Computing - PPGC Federal University of Pelotas - UFPel Pelotas Brazil

H.266/NVC is the current state-of-the-art video coding format, launched in 2020. Despite its high capability to compress video, including ultra-high definition content, royalty costs may prevent its wide adoption. The AOMedia video 1 (AV1) format is an alternative with competitive coding efficiency, besides being a royalty-free format. However, migrating legacy content from one format to another is a costly task, which requires long processing times. This work presents a solution for accelerating the H.266/NVC-to-AV1 trans coding based on machine learning. Twelve decision tree models trained with data gathered during the H.266NVC decoding and the AV1 encoding processes are proposed and implemented in the libaom reference software, leading to a complexity reduction of 12.60 % at the cost of coding efficiency losses of 1.81 % on average. To the best of the authors' knowledge, this is the first H.266NVC-to-AV1 trans coding acceleration solution published in the literature.

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Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication

Efficient Hardware Design for the VVC Affine Motion Compensa...

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IEEE Computer Society Annual Symposium on VLSI

作者： Marcello M. Muñoz Denis Maass Murilo Perleberg Luciano Agostini Marcelo Porto Graduate Program in Computing - PPGC Video Technology Research Group - ViTech Federal University of Pelotas - UFPel Pelotas Brazil

The Affine Motion Estimation (AME) is a new and high-complexity task of the Versatile video Coding (VVC) standard. The AME requires the Affine Motion Compensation (MC) to be performed for 4$\times$ 4 subblocks, where one among 156-tap interpolation filters was adopted to interpolate each sample of the 4$\times$ 4 subblock according to the motion vector relative to this subblock. This work presents two dedicated hardware implementations for the Affine MC of the VVC standard, the first focusing on the reduction of power dissipation and the second on the area requirement. The ASIC synthesis results of these architectures for TSMC 40nm standard cells show an area requirement of 54. 43k gates and power dissipation of 12. 8mW for the power efficient variant, while for the hardware efficient, the area requirement is 21. 91k gates and power dissipation of 14.41mW.

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Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors

Energy-Efficient Hardware Architecture for VVC TZS Using App...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Rafael Ferreira Luciano Agostini Cláudio M. Diniz Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas RS Brazil Microelectronics Group (GME) Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This paper investigates the impact of approximate subtractors in the hardware architecture of the Sum of Absolute Differences (SAD) computation within the Test Zone Search (TZS) algorithm, commonly used in current video encoders like the Versatile video Coding (VVC). Four state-of-the-art imprecise subtractors $(AppS, AXSC1, AXSC2, AXSC3)$ were analyzed across various video resolutions to assess their influence on computational effort, energy consumption, and coding efficiency. The results show that subtractors like $AppS_video$ and $AXCS1_video$ provide significant reductions in energy consumption with minimal impact on video coding quality. These findings are especially relevant for low-power devices and embedded systems, where energy efficiency is critical. The use of imprecise subtractors offers a promising tradeoff between computational efficiency and energy savings, making them a viable solution for high-performance video encoders.

关键词： video coding Energy consumption Embedded systems Energy conservation Energy resolution Computer architecture Energy efficiency Hardware Computational efficiency Power dissipation

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Multi-Objective optimized Complexity Control for the AV1 video Encoder

Multi-Objective optimized Complexity Control for the AV1 Vid...

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Picture Coding Symposium, PCS

作者： Gustavo Rehbein Isis Bender Guilherme Corrêa Luciano Agostini Marcelo Porto Federal University of Pelotas (UFPel) – Graduate Program in Computing (PPGC) Video Technology Research Group (ViTech)

ISBN: (纸本)9781665492584

AOMedia video 1 (AV1) is an open-source video encoding format launched in 2018 by Alliance for Open Media. To achieve high coding efficiency, AV1 brings significant innovations in comparison to its predecessor, the VP9 format. However, this came at the cost of a higher encoding complexity due to the newly introduced tools and block partitioning structures. To allow for wide deployment of AV1 in different multimedia devices, adjusting its encoding process according to the available computational resources is strongly desirable. Thus, this work presents an adaptive complexity controller for the AV1 encoder based on multi-objective optimization. Experimental results show that the proposed controller reduces encoding complexity in a target range from 10% to 40%, with satisfactory precision varying between 0.04 and 4.10 percentage points, and a BD-Rate between 0.22% and 5.24%.

关键词： Technological innovation Costs Sensitivity analysis Operating systems video sequences Focusing Media

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Alternative Reference Samples to Improve Coding Efficiency for Parallel Intra Prediction Solutions

Alternative Reference Samples to Improve Coding Efficiency f...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Iago Storch Nuno Roma Daniel Palomino Sergio Bampi Graduate Program in Computing Institute of Informatics Federal University of Rio Grande do Sul Porto Alegre Brazil INESC-ID Instituto Superior Técnico Universidade de Lisboa Lisboa Portugal Video Technology Research Group Graduate Program in Computing Federal University of Pelotas Pelotas Brazil

Exploring massive parallelism is a common strategy to mitigate the processing time of modern video encoding standards. Nonetheless, the existing data dependencies in some encoding tools pose difficult challenges to exploit such parallelism, especially during intra prediction, where the reconstructed adjacent blocks are used as references. Although some works made use of different reference samples to allow block-level parallelism in intra prediction, their proposals do not consider the variations caused by different bitrates, leading to some degradation in the output sequence. To deal with multiple bitrates more properly, this work proposes the application of image smoothing techniques to generate alternative reference samples that better represent the nuances of different bitrates. Experimental validations demonstrate that these improved references provide coding efficiency gains while still offering an equivalent parallelization opportunity.

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Fast Intra Mode Decision Using Machine Learning for the Versatile video Coding Standard

Fast Intra Mode Decision Using Machine Learning for the Vers...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Adson Duarte Bruno Zatt Guilherme Correa Daniel Palomino Video Technology Research Group (ViTech) Graduate Program in Computer Science (PPGC) Federal University of Pelotas (UFPel) Pelotas Brazil

This paper presents a fast intra mode decision solution for the VVC standard using machine learning. The idea is to reorder the evaluation of modes performed by the Rate-Distortion Optimization (RDO) process according to the modes occurrence rate. Based on the new evaluation order, three Decision Tree models were trained to skip the modes less likely to be chosen. The results show that the proposed solution achieves time savings of up to 15.57% with coding efficiency degradation of only 0.41% on average. When compared with related works, the proposed solution shows competitive results.

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