One of the new tools included in the AV1 video codec is the adaptive filtering scheme used in the sample interpolation process. This scheme includes three different filter families called Regular, Sharp and Smooth, of...
One of the new tools included in the AV1 video codec is the adaptive filtering scheme used in the sample interpolation process. This scheme includes three different filter families called Regular, Sharp and Smooth, offering high flexibility for motion estimation (ME) and motion compensation (MC). However, the high number of interpolation filters also leads to greater complexity and energy consumption, since the generation of samples at sub-pixel position is a costly process. This paper proposes a low-power and high-throughput hardware accelerator focused on the AV1 interpolation filters called Multiversion Interpolation Processor (MVIP). The accelerator includes the three AV1 interpolation filter families, with versions that employ operand isolation for power reduction in unused filters. The accelerator also includes a precise MVIP assuming the MC scenario, besides two approximate versions to reduce the cost on the ME scenario. The proposed design is able to process 8K video at 50fps in MC and 2,656.14 Msamples/sec in ME, with a power dissipation of 41.30mW.
This paper presents a fast Affine Motion Estimation (AME) of Versatile video Coding (VVC) Standard, based on Machine Learning and using Random Forest (RF) classification method. This encoding approach develops an RF m...
This paper presents a fast Affine Motion Estimation (AME) of Versatile video Coding (VVC) Standard, based on Machine Learning and using Random Forest (RF) classification method. This encoding approach develops an RF model for each block size. The models were trained with information extracted during the VVC encoding process of the current, parent, and neighboring Coding Units (CU). Each model is applied to predict whether the Affine Motion Estimation (AME) will be skipped or not for that CU size. The proposed solution achieves a reduction of 20% on average in AME encoding time, with an insignificant impact of 0.07% on BD-BR.
video transcoding for bit rate adaptation has become mandatory for over-the-top applications that deliver multimedia content in heterogeneous environments under different network conditions and user capabilities. As t...
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ISBN:
(数字)9789082797053
ISBN:
(纸本)9781728150017
video transcoding for bit rate adaptation has become mandatory for over-the-top applications that deliver multimedia content in heterogeneous environments under different network conditions and user capabilities. As transcoding requires sequentially decoding and re-encoding the video bitstream, the computational cost involved in the process is too high, especially when considering current state-of-the-art codecs, such as the High Efficiency video Coding (HEVC). This work presents a fast HEVC transcoder for bit rate adaptation based on Prediction Unit (PU) mode inheritance, which uses information gathered from the HEVC decoding process to accelerate PU mode decision in the re-encoding process. Experimental results show that the proposed method achieves an average transrating time reduction of 42% at the cost of a bitrate increase of 0.54%.
The Versatile video Coding (VVC) standard introduced several novel encoding tools for intra frame prediction, increasing the encoder complexity when compared to previous standards. Among these novelties is the MIP too...
The Versatile video Coding (VVC) standard introduced several novel encoding tools for intra frame prediction, increasing the encoder complexity when compared to previous standards. Among these novelties is the MIP tool, whose acceleration has not been tackled in the literature. Therefore, an efficient parallelization of MIP prediction targeting GPU platforms is now proposed. The presented technique makes use of alternative reference samples and computes the distortion in an approximate manner to expose and potentiate massive parallelism. Moreover, the adopted prediction scheduling and memory communication were tailored by considering the GPUs' architecture and memory hierarchy. When compared with a CPU execution, this work is capable to accelerate the MIP prediction up to 105 times at the cost of a negligible coding efficiency loss of 0.284 % BD-BR.
Developed by the AOMedia industry consortium, the AOM video 1 (AV1) is an open-source and royalty-free video encoder released in June 2018. The Constrained Directional Enhancement Filter (CDEF) is one of the three AV1...
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This work presents an Equirectangular projection (ERP) based Coding Tree Unit (CTU) splitting early termination algorithm for the High Efficiency video Coding (HEVC) intra prediction of 360-degree videos. The proposed...
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ISBN:
(数字)9781728180687
ISBN:
(纸本)9781728180694
This work presents an Equirectangular projection (ERP) based Coding Tree Unit (CTU) splitting early termination algorithm for the High Efficiency video Coding (HEVC) intra prediction of 360-degree videos. The proposed algorithm adaptively employs early termination in the HEVC CTU splitting based on distortion properties of the ERP projection, that generate homogeneous regions at the top and bottom portion of a video frame. Experimental results show an average of 24% time saving with 0.11% coding efficiency loss, significantly reducing the encoding complexity with minor impacts in the encoding efficiency. Besides, solution presents the best results considering the relation between time saving and coding efficiency when compared with all related works.
The Versatile video Coding standard was finalized by the Joint video Exploration Team in July 2020 and is currently considered the state-of-the-art video compression technology. VVC significantly improves coding effic...
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ISBN:
(纸本)9781728192017;9781728192024
The Versatile video Coding standard was finalized by the Joint video Exploration Team in July 2020 and is currently considered the state-of-the-art video compression technology. VVC significantly improves coding efficiency compared to HEVC thanks to several new features and tools that incur a large increase in computational cost. This paper presents a complexity and coding efficiency assessment of VVC divided into three analyses, focusing on: (1) the impact of using SIMD optimizations in the VVC Test Model software, (2) the impact of limiting partitioning structures when encoding, and (3) the computational cost associated to each encoding tool in VVC. Experimental results show that SIMD optimizations accelerate the encoding time by 40%, on average, and that limiting the available partitioning structures can decrease encoding time between 40% and 73%. The software profiling revealed that inter-frame prediction is responsible for almost half of the total encoding time. Finally, the paper also presents an analytic discussion on tools and partitioning possibilities that are rarely chosen in the mode decision process despite their high impact in coding complexity.
Developed by the AOMedia industry consortium, the AOM video 1 (AV1) is an open-source and royalty-free video encoder released in June 2018. The Constrained Directional Enhancement Filter (CDEF) is one of the three AV1...
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ISBN:
(数字)9781728133201
ISBN:
(纸本)9781728133218
Developed by the AOMedia industry consortium, the AOM video 1 (AV1) is an open-source and royalty-free video encoder released in June 2018. The Constrained Directional Enhancement Filter (CDEF) is one of the three AV1 in-loop filters and it is the focus of this work. The CDEF has the goal to reduce ringing artifacts generated with the encoding process, acting as a directional deringing filter. This paper presents a hardware design for the AV1 CDEF targeting real-time processing of 4K Ultra High Definition (UHD) videos. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 185 kgates and with a power dissipation of 43 mW when running at 93 MHz, reaching the frame rate of 60 frames per second (fps). To the best of the author's knowledge, there is no other work in the literature with dedicated hardware design for the AV1 CDEF.
AOMedia video 1 (AV1), developed by the Alliance for Open Media consortium and released in 2018, is an open-source and royalty-free video format. It was designed to deliver substantial compression gains over its prede...
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ISBN:
(数字)9781728133201
ISBN:
(纸本)9781728133218
AOMedia video 1 (AV1), developed by the Alliance for Open Media consortium and released in 2018, is an open-source and royalty-free video format. It was designed to deliver substantial compression gains over its predecessor VP9 whilst keeping hardware feasibility and a practical decoding complexity. When compared to state-of-the-art formats, AV1 has more complex encoder tools, including the intra prediction which is the focus of this work. This paper presents a highly parallelized ASIC solution for the directional intra prediction module. It supports all 56 directional modes defined in AV1 and is able to process all combinations of block partitions. When synthesized to the TSMC 40nm technology with a target frequency of 1,296MHz, the proposed design used an area of 455.8K gates and showed a power dissipation and energy consumption per predicted sample of 40.92mW and 0.055pJ/sample, respectively. The reached throughput supports the processing of 60 frames per second for UHD 4K videos (3840×2160 pixels). No other work was found in the literature with a hardware design supporting the AV1 intra prediction directional modes.
This paper presents a low-power and high-performance hardware design for the Depth Modeling Mode 1 (DMM-1) of the 3D-High Efficiency video Coding (3D-HEVC). The designed architecture is based on a low-complexity algor...
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ISBN:
(数字)9781728134277
ISBN:
(纸本)9781728134284
This paper presents a low-power and high-performance hardware design for the Depth Modeling Mode 1 (DMM-1) of the 3D-High Efficiency video Coding (3D-HEVC). The designed architecture is based on a low-complexity algorithm developed to reduce the DMM-1 computational effort and to avoid the use of memory. The architecture was described in VHDL, and the ASIC synthesis was performed for the TSMC 40nm technology. The synthesis results showed a gate count of 1,283k gates and a power dissipation of 51.36 mW, when running at 82 MHz. The designed architecture is capable of processing 3D 1080p videos with up to 11 views at 30 frames per second. The reached results surpass the published works in terms of throughput and power dissipation.
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