This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers,...
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This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature. The architecture is simple, modular, and cascadable, and has been implemented in VLSI. Experimental results show that real-time coefficient calculation on a 512/spl times/512 monochrome video input can be achieved with 1.2 /spl mu/m technology.
Video compression is becoming increasingly important in several applications. Vector quantization (VQ) is a powerful technique for very low bit rate image/video compression and is an attractive technique for mobile mu...
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Video compression is becoming increasingly important in several applications. Vector quantization (VQ) is a powerful technique for very low bit rate image/video compression and is an attractive technique for mobile multimedia applications. Adaptive VQ techniques provide an excellent coding performance at the expense of significant increases in computational complexity making real-time implementation difficult. We propose a VLSI chip-set design to implement a high performance cache based (adaptive) VQ (CVQ) technique using VHDL for real-time video compression.
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