Performance of advanced hybrid-gate CMOS (poly-Si/HfSiON nMIS and poly-Si/TiN/HfSiON pMIS) is demonstrated. V th of pMIS is controlled by fluorine implantation and by PVD/CVD-stacked TiN, which has higher WF than con...
详细信息
ISBN:
(纸本)4900784036;97
Performance of advanced hybrid-gate CMOS (poly-Si/HfSiON nMIS and poly-Si/TiN/HfSiON pMIS) is demonstrated. V th of pMIS is controlled by fluorine implantation and by PVD/CVD-stacked TiN, which has higher WF than conventional single-CVD TiN. This combination enables sufficient V th -control without degradation of device characteristics by excessive fluorine. Performance boosters such as strain enhancement techniques and laser annealing are easily and successfully introduced, and high current drivability is obtained. This advanced hybrid structure is promising for CMIS platforms of 45-nm node and beyond.
The surface state of copper after an etching process using CF4 gas has been analyzed. Copper surface stability against corrosion is evaluated through a storage test performed under high-humidity conditions after the e...
详细信息
We have investigated the changes of chemical bonding states of an H-terminated silicon surface under inert gas (Ar,N-2) and ultrahigh vacuum (UHV) annealing using X-ray photoelectron spectroscopy (XPS) and thermal des...
详细信息
We have investigated the changes of chemical bonding states of an H-terminated silicon surface under inert gas (Ar,N-2) and ultrahigh vacuum (UHV) annealing using X-ray photoelectron spectroscopy (XPS) and thermal desorption spectroscopy (TDS). SiC is formed (corresponding to similar to0.1 monolayer) under inert gas and UHV annealing at around 500degreesC, which is coincident with the temperature of the dangling bonds formation at the silicon surface by hydrogen desorption, whereas SiC is not formed under O-2 annealing. From the precise analysis using a combination of XPS and TDS, the SiC formation is related to the reaction between the silicon surface and the organic contamination that is unavoidably adsorbed during air exposure. We also studied the electrical properties of metal oxide semiconductor capacitors with a chemical vapor deposited silicon oxide gate insulator formed on Ar- and O-2-annealed silicon surfaces. At preannealing increases the leakage current by approximately 10(-4) times compared with O-2 annealing. (C) 2005 The Electrochemical Society.
Gate dielectric as thin as E0T=1.6nm or below is required for 65nm CMOS devices according to ITRS (2003). High-k materials such as HfSiON with satisfactory low leakage are expected as an alternative gate dielectric. H...
详细信息
Gate dielectric as thin as E0T=1.6nm or below is required for 65nm CMOS devices according to ITRS (2003). High-k materials such as HfSiON with satisfactory low leakage are expected as an alternative gate dielectric. However, two big problems have been revealed in the use of HfSiON gate dielectric; (i) Reduction of effective carrier mobility (/spl mu//sub eff/) in scaled EOTs and (ii) high K, in pFETs as stated in C. Hobbs et al. (2003) and L.-A. Ragnarsson et al. (2003). Here, we propose Hf-profile engineering; higher Hf concentration near the gate electrode and lower near the substrate for improving degraded /spl mu//sub eff/. Combination of metal-Hf PVD on interface layer (IL) with precise thickness control and post oxidation is a suitable technique to form such Hf-profile engineered HfSiON (HPE-HfSiON) films. In order to lower K, in pFETs, we present forward-bias technique as presented in M. Miyazaki et al. (2002).
In this study, we used direct nitridation technique using N/sub 2/ plasma to from ultra-thin SiN gate dielectric and successfully fabricated poly-Si gate CMOS device with mass production compatible fabrication flow in...
详细信息
In this study, we used direct nitridation technique using N/sub 2/ plasma to from ultra-thin SiN gate dielectric and successfully fabricated poly-Si gate CMOS device with mass production compatible fabrication flow including source and drain silicidation and 1050/spl deg/C spike anneal. We also studied these SiN gate dielectrics from reliability including dielectric breakdown.
A most preferable candidate of gate dielectrics in advanced CMOS to satisfy the requirement of an ITRS roadmap is still SiON, especially for high-performance and low-power devices. To advance the efficiency of SiON ga...
详细信息
A most preferable candidate of gate dielectrics in advanced CMOS to satisfy the requirement of an ITRS roadmap is still SiON, especially for high-performance and low-power devices. To advance the efficiency of SiON gate dielectrics, the keyword is N-rich. A high nitrogen concentration leads to low leakage current and high immunity to impurity penetration. However, in N-rich SiON, the mobility degradation and NBTI enhancement due to fixed charges formed by incorporated nitrogen atoms near the interface are problems. To solve these problems, we developed a SiN gate dielectric with an oxygen-enriched interface (OI-SiN). A process in which oxygen atoms are incorporated after forming SiN provides enhanced nitrogen concentration and an oxygen-enriched interface while simultaneously suppressing fixed charges, even in dielectrics having sub-nm EOT. This OI-SiN has good immunity against impurity penetration and provides superior device performance compared to the conventional SiON. Furthermore, the OI-SiN was much effective as an interfacial layer of high-K gate stack to solve problems in high-K gate dielectric.
暂无评论