The Gemini system is a replicated-file testbed facility designed for local area networks and is built using ordinary host unix machines. Gemini was designed to test empirically consistency and recovery schemes for rep...
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The Gemini system is a replicated-file testbed facility designed for local area networks and is built using ordinary host unix machines. Gemini was designed to test empirically consistency and recovery schemes for replicated files in a distributed environment. A principle objective is to protect files against a fixed number of host and network failures while maintaining consistent data. Gemini replicated files are implemented as several copies of ordinary files that reside on distinct hosts. We present the Gemini system testbed design and discuss three consistency and recovery schemes: voting with witnesses, dynamic voting, and semisynchronous voting. Empirical and analytic performance results are presented.
This paper presents the results of extensive numerical testing of a second-order OPF solution method. The testing was conducted using a 1500 bus network under various loading conditions. Three issues were studied: ...
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An efficient algorithm that enumerates parses of ambiguous context-free languages is described, and its time and space complexities are discussed. When context-free parsers are used for natural language parsing, patte...
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Static CMOS circuits can fail in ways that make the traditional stuck-at fault model and test generation techniques inadequate. It will be shown that the layout of these circuits can affect testability and in some cas...
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The design issues in implementing an integrated voice, data, and video services system on a token ring network are discussed. The presence of real-time traffic, namely voice, on the same network makes the implementati...
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The design issues in implementing an integrated voice, data, and video services system on a token ring network are discussed. The presence of real-time traffic, namely voice, on the same network makes the implementation complicated. The performance requirements of these traffic types are different. Voice creates stream traffic on a network, whereas data traffic is bursty. Voice packets need to be delivered within a limited time interval, whereas the data emphasizes error-free delivery. A possible solution, supported by a simulation study, is discussed.< >
The read and write availabilities of replicated data managed by the regeneration algorithm, a replica control protocol based on file regeneration, are evaluated, and two regeneration protocols are presented that overc...
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The read and write availabilities of replicated data managed by the regeneration algorithm, a replica control protocol based on file regeneration, are evaluated, and two regeneration protocols are presented that overcome some of its limitations. The first protocol combines regeneration and the available copy approach to improve availability of replicated data. The second combines regeneration and the dynamic voting approach to guarantee data consistency in the presence of network partitions while maintaining a high availability. Expressions for the availabilities of replicated data managed by both protocols are derived and found to improve significantly on the availability achieved using extant consistency protocols.< >
A research project at Iowa State University to investigate the use of a high-speed, byte-serial bus to implement a multiple-bus interconnection network for a fine-grain parallel architecture is discussed. The project ...
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A research project at Iowa State University to investigate the use of a high-speed, byte-serial bus to implement a multiple-bus interconnection network for a fine-grain parallel architecture is discussed. The project focuses on the electrical properties of the bus, high-speed serial transmission, and bus contention resolution. Prototypes were developed to test critical aspects of the design, and the network was simulated to analyze its performance within the context of the parallel architecture. Results indicate that the network can effectively interconnect many processors (64) with relatively few buses (5), thereby giving a low packplane line count. By making a uniform bus that sent bytes at a rate limited only by clock skew, it was possible to increase the information transmission rate on a line by a factor of 4-10 over a conventional bus. This allowed for several high-speed buses with a limited pin count. It is concluded that multiple-bus networks offer the connectivity and bandwidth of a crossbar switch at a reasonable implementation cost.< >
This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information...
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This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information about the design such as the structure, regularity, functionality, and control signals in the generation process. New algorithms are proposed and have been implemented for combinational modules and bus structures. A significant speedup has been obtained for these modules of a commercially available chip.
The authors describe a frequency-scanned microstrip array antenna developed for the University of Massachusetts' airborne C-band scatterometer system. The antenna is a linearly polarized array consisting of 16 ser...
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The authors describe a frequency-scanned microstrip array antenna developed for the University of Massachusetts' airborne C-band scatterometer system. The antenna is a linearly polarized array consisting of 16 series-fed E-plane columns each with 27 microstrip patch radiating elements. A schematic of the antenna radiating surface is presented, and frequency-scanned radiation patterns are shown.< >
Timing verification is a critical part of VLSI circuit design. A new approach to timing verification using Register Transfer Level (RTL) descriptions is presented, which eliminates false paths that occur due to (i) re...
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(纸本)9780897913102
Timing verification is a critical part of VLSI circuit design. A new approach to timing verification using Register Transfer Level (RTL) descriptions is presented, which eliminates false paths that occur due to (i) redundancy, (ii) reconvergent fanout or (iii) control signal constraints, and generates a test for the critical paths. High level instructions of the circuit are used to test for any timing violations. An algorithm to identify a minimal set of instructions that tests the circuit for all timing errors in valid paths is proposed. Results are presented based on an implementation of the algorithm in LISP programming language on a TI Explorer machine.
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