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Custom Integrated Circuits Conference (CICC)

作者： M.E. Levitt J.A. Abraham Computer Systems Group Coordinated Science Lab University of Illinois Urbana IL USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

Static CMOS circuits can fail in ways that make the traditional stuck-at fault model and test-generation techniques inadequate. It is shown that the layout of these circuits can affect testability and in some cases reduce the number of possible faults in a design. A method is presented to analyze circuits at the symbolic layout level and to enhance testability using local transformations. A set of standard cells was designed using the layout level techniques. These standard cells are used in the MIS synthesis system to design over 100 example circuits. It is shown that the modified designs enable stuck-at tests to achieve significantly higher stuck-open fault coverage with an overhead that can be easily estimated. A synthesis strategy is presented to design easily testable random logic circuits

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Modeling the atmosphere as an unguided optical communications channel

Modeling the atmosphere as an unguided optical communication...

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IEEE International Conference on Communications (ICC)

作者： R.M. Nuber K.S. Shanmugan TRW Electronics Systems Group Redondo Beach CA USA Department of Electrical and Computer Engineering University of Kansas Lawrence KS USA

The authors propose a system-level model for simulating the Earth's atmosphere as an unguided optical communications channel. The major degradations in received optical intensity introduced by the atmosphere are scintillation, beam spreading, beam wander, and atmospheric transmissivity. The model presented considers scintillation and beam wander to impose random fading in the received signal while beam spreading is a constant loss in intensity. Atmospheric transmissivity is treated as a filterlike channel transfer function. Relationships for the parameters of the model are given in terms of parameters which characterize the optical link. Also included is a description of an implementation of the model. The implementation discussed is being integrated into an end-to-end simulator for a direct-detention laser communication system operating in the atmosphere.< >

关键词： Atmospheric modeling Communication channels Degradation Optical receivers Optical transmitters Optical filters Optical fiber communication Terrestrial atmosphere Optical propagation Laser modes

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A Novel Approach to Accurate Timing Verification Using RTL Descriptions

A Novel Approach to Accurate Timing Verification Using RTL D...

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Design Automation Conference

作者： K. Roy J.A. Abraham Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

Timing verification is a critical part of VLSI circuit design. A new approach to timing verification using Register Transfer Level (RTL) descriptions is presented, which eliminates false paths that occur due to (i) redundancy, (ii) reconvergent fanout or (iii) control signal constraints, and generates a test for the critical paths. High level instructions of the circuit are used to test for any timing violations. An algorithm to identify a minimal set of instructions that tests the circuit for all timing errors in valid paths is proposed. Results are presented based on an implementation of the algorithm in LISP programming language on a TI Explorer machine.

关键词： Timing Testing Permission Clocks Counting circuits Distributed computing Machinery Instruments Design automation Heuristic algorithms

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Data detection and timing recovery for a noncoherent discriminator-based GMSK receiver

Data detection and timing recovery for a noncoherent discrim...

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IEEE Conference on Vehicular Technology (VTC)

作者： M.S. El-Tanany H.P. Stern S.A. Mahmoud Department of Systems and Computer Engineering Carleton University Ottawa Canada Mobile Communications Research Group ElectroCom Automation Inc. Arlington TX USA

The authors examine the effect of various B/sub t/T,h combinations (B/sub t/=premodulation filter bandwidth T=bit period, h=modulation index), various IF (intermediate frequency) filter types, and various IF filter bandwidths on the performance of a noncoherent GMSK (Gaussian minimum-shift keying) receiver. Numerical results are presented for bit error rate (BER) performance of the data detection subsystem and for phase jitter within the timing recovery subsystem. Results show that BER is very sensitive to IF filter type and bandwidth and that phase jitter is very sensitive to IF filter bandwidth. The test practical IF filter for the noncoherent GMSK receiver is a phase-equalized Butterworth filter. A filter order of 6 or 8 poles is sufficient for noise rejection, but higher order may be required to satisfy adjacent channel interference requirements. Although data detector performance is optimized with an IF filter bandwidth of B/sub t/T=1.1, this increase in bandwidth does not significantly affect data detector performance.< >

关键词： Timing Detectors Bandwidth Bit error rate Frequency modulation Band pass filters Jitter Baseband Radio transmitters systems engineering and theory

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A test generation system for path delay faults

A test generation system for path delay faults

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： S. Patil S.M. Reddy Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana IL USA Department of Elect. and Comp. Engineering University of Iowa Iowa IA USA

A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the number of lines in the network, criteria and efficient algorithms to prune the number of paths for test generation are presented. The test generation system is evaluated using the ISCAS combinational benchmark circuits.< >

关键词： System testing Delay systems Circuit testing Circuit faults Logic testing Propagation delay Clocks Test pattern generators Logic circuits Sequential circuits

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A design technique for optimal bandpass filters

A design technique for optimal bandpass filters

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IEEE Southeastcon

作者： G.W. Medlin J.W. Adams Electrical and Computer Engineering University of South Carolina Columbia SC USA Radar Systems Group Hughes Aircraft Company Los Angeles CA USA Electrical Engineering California State University Northridge CA USA

An approach to the design of linear-phase FIR (finite impulse response) bandpass filters is presented. Their design is based on the minimization of the integrated square error for the frequency response while maintaining maximal flatness at the passband center. The closed-form solution for the filter coefficients is obtained by the method of Lagrange multipliers. A design example is included which demonstrates the effectiveness of the technique.< >

关键词： Band pass filters Passband Finite impulse response filter Frequency response Filtering theory Nonlinear filters Digital filters computer errors Airborne radar Aircraft

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Portable parallel logic and fault simulation

Portable parallel logic and fault simulation

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IEEE International Conference on computer-Aided Design

作者： R.B. Mueller-Thuns D.G. Saab R.F. Damiano J.A. Abraham Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA IBM Thomas J. Watson Research Center Yorktown Heights NY USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

Consideration is given to the use of general-purpose multiprocessors for various simulation tasks. The aims of the work are to define a general framework for the parallel simulation of digital systems and to develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. Specifically, a novel partitioning approach is introduced and used as the basis for the parallel logic and fault simulation of synchronous gate-level designs. Performance experiments with prototype implementations on a message passing and a shared memory machine give promising results, in particular for fault simulation.< >

关键词： Logic Computational modeling Very large scale integration computer simulation Switches Circuit faults Circuit simulation Discrete event simulation Digital systems High performance computing

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A new design technique for maximally linear differentiators

A new design technique for maximally linear differentiators

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： G.W. Medlin J.W. Adams Electrical and Computer Engineering Department University of South Carolina Columbia SC USA Radar Systems Group Hughes Aircraft Company Los Angeles CA USA EE Department California State University Northridge CA USA

An approach to the design of linear-phase, maximally linear full-band and wideband differentiators with or without designated stopbands is proposed. The design is based on minimization of the integrated square error for the frequency response and is formulated as a quadratic programming problem with linear equality constraints. The closed-form solution is obtained by the method of Lagrange multipliers. Several design examples are included. They indicate significant improvement in low-frequency error when compared to similar designs based on the minimax criterion.< >

关键词： Finite impulse response filter Passband Linearity Frequency response Closed-form solution Wideband computer errors Lagrangian functions Minimax techniques Vectors

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Volumes of human learning on machine learning

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Nature 1989年第6205期337卷 315-315页

作者： Max Bramer Manager of the Knowledge Engineering Programme Hewlett-Packard Laboratories Stoke Gifford Bristol UK Chairman of the British Computer Society's Specialist Group on Expert Systems

Proceedings of the Fifth International Conference on Machine *** by John Laird. Morgan Kaufmann: 1988. Pp. 467. Pbk $24.95. In Britain distributed by Afterhurst, 116 Pentonville Road, London NW1 9JB, £*** 88: Proceedings of the Third European Working Session on Learning. Edited by Derek Sleeman. Pitman: 1988. Pp. 263. Pbk £25.

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THE AEGIS DATA BUS EXPERIMENT

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NAVAL ENGINEERS JOURNAL 1989年第5期101卷 53-58页

作者： FRINK, JG VERVEN, DM John G. Frink is an assistant group supervisor in the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He received his B.S. degree in physics from Michigan State University in 1968 and the M.S. degree in computer science from the University of Maryland in 1971. Mr. Frink worked at the Naval Surface Weapons Center White Oak Laboratory on a variety of weapons systems before joining the Applied Physics Laboratory in 1978. Mr. Frink has supervised the development of a large scale battle group simulation that successfully employs the receiver selection paradigm described herein on a hardware suite composed of an extensible number of (currently 15) processors. David M. Verven is a senior electrical engineer in the Fleet Systems Department of The Johns Hopkins University Applied Physics Laboratory. He received the B.S. degree in electrical engineering from the University of Maryland College Park in 1979 and the M. S. degree in the same discipline from The Johns Hopkins University in 1984. Mr. Verven joined the Applied Physics Laboratory in 1979 and initially worked on analysis of Navy sensor systems. In 1981 he was the AN/SPS-49 test team leader for the New Threat Upgrade (NTU) combat system land-based test. In 1982 he became involved in the development of the BBWRS system. Currently he is involved in real-time computer program development for the CEP project.

This paper documents an experiment performed by The Johns Hopkins University Applied Physics Laboratory to measure the effect of inserting a data bus into a combat system. The experiment was conducted at the Aegis computer Center located at the Naval Surface Weapons Center in Dahlgren, Virginia (NSWC/DL). The purpose of the experiment was to determine whether or not the Aegis Weapon System (the core of the Aegis Combat System) could be operated with a portion of its point-to-point interelement cables replaced by a data bus. The data bus chosen for the experiment employs message broadcasting with receiver selection. A primary goal of the experiment was to minimize the amount of Aegis computer program changes required to accommodate the data bus. The results presented in this paper will show that the experiment was a success. Key certification tests were passed with no computer program changes to the tactical elements and minimal changes in the Aegis tactical executive (ATES) program (less than 110 words changed).

关键词： Data Transmission Equipment

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