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Towards incremental test suite optimization for software product lines 14

Towards incremental test suite optimization for software pro...

引用

6th International Workshop on Feature-Oriented Software Development, FOSD 2014

作者： Baller, Hauke Lochau, Malte Institute for Programming and Reactive Systems Braunschweig Germany Real-time Systems Lab Darmstadt Germany

ISBN: (纸本)9781450329804

The design of an appropriate test suite for software testing is a challenging task. It requires a suitable tradeoff between effectiveness, e.g., a suficient amount of test cases to satisfy the test goals of a given coverage criterion, and eficiency, e.g., a redundancy-reduced selection of test cases. Recent test suite optimization approaches, therefore, usually require an explicit enumeration of existing test cases to select from. The test suite design for covering entire software product lines is even more problematic as the dependency between test cases, test goals and product configurations has to be taken into account. Due to the exponential number of configurations w.r.t. the number of features, an explicit enumeration of all products for optimizing a product-line test suite is impractible. To tackle this problem, we propose an incremental test suite optimization approach for product-line testing that does not require an explicit representation of the set of configurations under test, but rather uses a symbolic representation in terms of feature constraints. The approach is illustrated by means of a running example. © Copyright 2014 ACM.

关键词： Software testing

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Just-In-Time Software Pipelining 14

Just-In-Time Software Pipelining

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Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization

作者： Hongbo Rong Hyunchul Park Youfeng Wu Cheng Wang Programming Systems Lab Intel Labs

ISBN: (纸本)9781450326704

Software pipelining exploits instruction-level parallelism from loops. In static compilers, it has been one of the most efficient optimizations for wide-issue architectures. However, the compilation time is at least O(|V|3) (V: the set of operations in a loop) and in the worst-case exponential. This paper extends software pipelining to dynamic compilers. We present a novel and simple algorithm with linear time O(|V| + |E|) (E: the set of edges in the dependence graph of a loop). Preliminary experiments show the method is light-weight and generates optimal or near-optimal schedules.

关键词： Just-In-Time Compilation Dynamic Optimization Software Pipelining Dynamic Compiler Scheduling

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AccelDroid: Co-designed Acceleration of Android Bytecode

AccelDroid: Co-designed Acceleration of Android Bytecode

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11th IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

作者： Wang, Cheng Wu, Youfeng Cintra, Marcelo Programming Systems Lab Microprocessor and Programming Research Intel Labs

ISBN: (纸本)9781467355254;9781467355247

A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations. It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite.

关键词： Linux hardware-software codesign instruction sets program compilers virtual machines

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Multi-Objective Test Suite Optimization for Incremental Product Family Testing

Multi-Objective Test Suite Optimization for Incremental Prod...

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IEEE International Conference on Software Testing, Verification and Validation

作者： Hauke Baller Sascha Lity Malte Lochau Ina Schaefer TU Braunschweig Institute for Programming and Reactive Systems TU Darmstadt Real Time Systems Lab TU Braunschweig Institute of Software Engineering and Automotive Informatics

ISBN: (纸本)9781479922567

The design of an adequate test suite is usually guided by identifying test requirements which should be satisfied by the selected set of test cases. To reduce testing costs, test suite minimization heuristics aim at eliminating redundancy from existing test suites. However, recent test suite minimization approaches lack (1) to handle test suites commonly derived for families of similar software variants under test, and (2) to incorporate fine-grained information concerning cost/profit goals for test case selection. In this paper, we propose a formal framework to optimize test suites designed for sets of software variants under test w.r.t. multiple conflicting cost/profit objectives. The problem representation is independent of the concrete testing methodology. We apply integer linear programming (ILP) to approximate optimal solutions. We further develop an efficient incremental heuristic for deriving a sequence of representative software variants to be tested for approaching optimal profits under reduced costs. We evaluated the algorithm by comparing its outcome to the optimal solution.

关键词： Testing Strategies Test Coverage of Specifications Constrained Optimization Linear programming

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HW/SW Co-designed Acceleration of Dynamic Languages

HW/SW Co-designed Acceleration of Dynamic Languages

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14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded systems

作者： Wu, Youfeng Programming Systems Lab United States

ISBN: (纸本)9781450320856

Dynamic programming Languages, such as Java, JavaScr ipt, PHP, Perl, Python, Ruby, etc., are dominating languages for programming the web. HW/SW co-designed virtual machine can significantly accelerate their executions by transparently leveraging internal HW features via an internal compiler. We also argue for a common API to interface dynamic languages with the HW/SW co-designed virtual machine, so that a single internal compiler can accelerate all major dynamic languages.

关键词： Languages Measurement Performance Dynamic languages Just-in-time Compilation HW/SW Co-designed Virtual Machine Acceleration

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Allocating rotating registers by scheduling 46

Allocating rotating registers by scheduling

引用

46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2013

作者： Rong, Hongbo Park, Hyunchul Wang, Cheng Wu, Youfeng Programming Systems Lab. Intel Labs. United States

ISBN: (纸本)9781450326384

A rotating alias register file is a scalable hardware support to detect memory aliases at run-time. It has been shown that it can enable instruction-level parallelism to be effectively exploited from sequential code. Yet it is unknown how to apply it to loops. This paper presents an elegant and efficient solution that allocates rotating alias registers for a software-pipelined schedule of a loop. We show that surprisingly, this specific register allocation problem can be reduced to another software pipelining problem, for which numerous efficient algorithms are available. This is interesting in both theory and practice. We propose an algorithmic framework to solve the problem. We also present a simple software pipelining algorithm that specially targets register allocation. Comparison with a few other algorithms shows that it usually achieves the best allocation at the least time cost. Finally, we generalize the approach to allocate general-purpose (integer/floating-point/predicate) rotating registers by showing that it is also a software pipelining problem. © 2013 ACM.

关键词： Scheduling

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Reducing higher-order theorem proving to a sequence of SAT problems

Reducing higher-order theorem proving to a sequence of SAT p...

引用

作者： Brown, Chad E. Programming Systems Lab Universität des Saarlandes Campus E1 3 66123 Saarbrücken Germany

We describe a complete theorem proving procedure for higher-order logic that uses SAT-solving to do much of the heavy lifting. The theoretical basis for the procedure is a complete, cut-free, ground refutation calculus that incorporates a restriction on instantiations. The refined nature of the calculus makes it conceivable that one can search in the ground calculus itself, obtaining a complete procedure without resorting to meta-variables and a higher-order lifting lemma. Once one commits to searching in a ground calculus, a natural next step is to consider ground formulas as propositional literals and the rules of the calculus as propositional clauses relating the literals. With this view in mind, we describe a theorem proving procedure that primarily generates relevant formulas along with their corresponding propositional clauses. The procedure terminates when the set of propositional clauses is unsatisfiable. We prove soundness and completeness of the procedure. The procedure has been implemented in a new higher-order theorem prover, Satallax, which makes use of the SAT-solver MiniSat. We also describe the implementation and give several examples. Finally, we include experimental results of Satallax on the higher-order part of the TPTP library. © 2013 Springer Science+Business Media Dordrecht.

关键词： Theorem proving

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Model-based dynamic optimization with openmodelica and CasADi

Model-based dynamic optimization with openmodelica and CasAD...

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7th IFAC Symposium on Advances in Automotive Control, AAC 2013

作者： Shitahun, Alachew Ruge, Vitalij Gebremedhin, Mahder Bachmann, Bernhard Eriksson, Lars Andersson, Joel Diehl, Moritz Fritzson, Peter PELAB-Programming Environment Lab Dept. Computer Science Linköping University SE-581 83Linköping Sweden Dept. Mathematics and Engineering University of Applied Sciences D-33609 Bielefeld Germany Vehicular Systems Dept. Electrical Engineering Linköping University SE-581 83 Linköping Sweden K.U. Leuven Belgium

ISBN: (纸本)9783902823434

This paper demonstrates model-based dynamic optimization through the coupling of two open source tools: OpenModelica, which is a Modelica-based modeling and simulation platform, and CasADi, a framework for numerical optimization. The coupling uses a standardized XML format for exchange of differential-algebraic equations (DAE) models. OpenModelica supports export of models written in Modelica and the optimization language extension using this XML format, while CasADi supports import of models represented in this format. This allows users to define optimal control problems (OCP) using Modelica and optimization language specification, and solve the underlying model formulation using a range of optimization methods, including direct collocation and direct multiple shooting. The proposed solution has been tested on several industrially relevant optimal control problems, including a dieselelectric power train.

关键词： Optimization

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From locks to correct and efficient transactional memory

From locks to correct and efficient transactional memory

引用

作者： Wang, Cheng Wu, Youfeng Programming Systems Lab Microprocessor and Programming Research Intel Labs 2200 Mission College Blvd. Santa Clara CA 95052 United States

Transactional memory addresses a number of important issues in lock-based parallel programs. Unfortunately, the semantics of transactions are different from those of critical sections defined by locks. The semantic differences make it difficult to correctly port existing lock-based programs to transaction-based programs. Experienced programmers accustomed to lock-based programming can easily make mistakes in transaction-based programming as parallel programs running correctly using locks can run incorrectly when critical sections are converted to using transactions. This problem becomes even more severe in porting lock-based programs to use the efficient software transactional memory. In this paper, we first identify three necessary properties in a program for the program execution using transactions to be equivalent to the program execution using locks. Assuming that the input lock-based program satisfies the necessary properties (i.e., a well-behaved parallel program), we next present a correctness condition to verify the transactional memory implementation in order for the program execution using transactions to be equivalent to the program execution using locks. Finally, we develop a correct and efficient software transactional memory implementation that satisfies the correctness condition so that locks in the well-behaved parallel programs can be converted to use the efficient software transactional memory easily and correctly. © 2012 World Scientific Publishing Company.

关键词： Locks (fasteners)

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Resource-oriented consistency analysis of engineering processes

Resource-oriented consistency analysis of engineering proces...

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14th International Conference on Enterprise Information systems, ICEIS 2012

作者： Bauer, Bernhard Eisenbarth, Thomas Frenzel, Christoph Honke, Benjamin Programming Distributed Systems Lab. Institute of Computer Science University of Augsburg Augsburg Germany

ISBN: (纸本)9789898565105

A number of popular engineering processes and methodologies emerged over the past years which attracted interest in research and industry. For process enactment, enterprises have to match requirements of engineering processes with existing resources. Therefore, it has to be analyzed if employees have sufficient skills or if infrastructure has sufficient capabilities to match the requirements of a situational process. Both, maintaining a skill and resource database and matching requirements against this database are an enormously challenging and time-consuming task. Additionally, this matching has to be carried out regularly as employees join and leave the company and skills change over time. Based upon a formal, logical base, we present an approach that combines ontological and metamodeling technical spaces and enables an automatic analysis of engineering processes regarding the existence of necessary resources.

关键词： Ontology

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