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Practical weak-atomicity semantics for Java STM 08

Practical weak-atomicity semantics for Java STM

引用

20th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA'08

作者： Menon, Vijay Adl-Tabatabait, Ali-Reza Balensiefer, Steven Hudson, Richard L. Shpeisman, Tatiana Saha, Bratin Welc, Adam Programming Systems Lab Intel Corporation Santa Clara CA 95054 Germany Department of Computer Science and Engineering University of Washington Seattle WA 98195 United States

ISBN: (纸本)9781595939739

As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transaction memory (TM) semantics are complicated by the fact that programs may access the same memory locations both inside and outside transactions. Strongly atomic semantics, where non-transactional accesses are treated as implicit single-operation transactions, remain difficult to provide without specialized hardware support or significant performance overhead. As an alternative, many in the community have informally proposed that a single global lock semantics [18, 10], where transaction semantics are mapped to those of regions protected by a single global lock, provide an intuitive and efficiently implementable model for programmers. In this paper, we explore the implementation and performance implications of single global lock semantics in a weakly atomic STM from the perspective of Java, and we discuss why even recent STM implementations fall short of these semantics. We describe a new weakly atomic Java STM implementation that provides single global lock semantics while permitting concurrent execution, but we show that this comes at a significant performance cost. We also propose and implement various alternative semantics that loosen single lock requirements while still providing strong guarantees. We compare our new implementations to previous ones, including a strongly atomic STM. [24] Copyright 2008 ACM.

关键词： Semantics

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Parallel programming environment: A key to translating tera-scale platforms into a big success 07

Parallel programming environment: A key to translating tera-...

引用

International Symposium on Code Generation and Optimization, CGO 2007

作者： Fang, Jesse Adl-Tabatabai, Ali Intel Programming Systems Lab.

ISBN: (纸本)0769527647

Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since the power and thermal constraints increase with frequency, multi-core or many-core will be the way of the future microprocessor. In the near future, HW platforms will have many-cores (>16 cores) on die to achieve >1 TIPs computation power, which will communicate each other through an ondie interconnect fabric with >1 TB/s on-die bandwidth and <30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and the optical silicon photonics will provide up to 1 Tb/s I/O bandwidth between boxes. The HW system with TIPs of compute power operating in Tera-bytes of data make this a "Tera-scale" platform. What are the SW implications with the HW changes from uniprocessor to Tera-scale platform with many-cores as "the way of the future?" It will be great challenge for programming environments to help programmers to develop concurrent code for most client software. A good concurrent programming environment should extend the existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are lots of research topics. Examples of these topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms like Transactional Memory to replace simple "Thread + Lock" structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with HW support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and SW tools in the concurrent programming environment. A more interesting problem is how to use such a many-core system to improve single-threaded performance. ©200

关键词： Parallel programming

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Parallel programming environment: A key to translating tera-scale platforms into a big success 07

Parallel programming environment: A key to translating tera-...

引用

2007 ACM SIGPLAN Symposium on Principles and Practice of Parallel programming, PPoPP'07

作者： Fang, Jesse Z. Programming Systems Lab. Intel Corporation

ISBN: (纸本)1595936025

Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since power and thermal constraints increase with frequency, multi-core or many-core microprocessors will be the way of the future. In the near future, hardware platforms will have sixteen or more cores on die to achieve more than one Tera Instructions Per second (TIPs) computation power. These cores will communicate each other through an on-die interconnect fabric with more than one TB/s on-die bandwidth and less than 30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and optical silicon photonics will provide up to one Tb/s I/O bandwidth between boxes. The hardware system with TIPs of compute power operating on terabytes of data make this a ?tera-scale? platform. What are the software implications with the hardware changes from uniprocessor to tera-scale platform with many cores as "the way of the future?" It will be a great challenge for programming environments to help programmers develop concurrent code for most client software. A good concurrent programming environment should extend existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are many research topics. Examples topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms such as Transactional Memory to replace simple ?Thread + Lock? structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with hardware support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and software tools in the concurrent programming environment. A more interesting proble

关键词： Parallel programming

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A survey on workflow annotation & composition approaches

A survey on workflow annotation & composition approaches

引用

Workshop on Semantic Business Process and Product Lifecycle Management, SBPM 2007 - Held in Conjunction with the 3rd European Semantic Web Conference, ESWC 2007

作者： Lautenbacher, Florian Bauer, Bernhard Programming Distributed Systems Lab. University of Augsburg Germany

Efficient business processes are key to economic success. With the need to frequently adapt or restructure business processes and workflows in a dynamic market, agile processes and (semi-)automatic workflow and process composition would be useful. Currently, this is a manual and time-consuming task. Automating and optimizing this task is of high interest in research communities. Nevertheless, the orientation differs: Some focus on semantic web services, others on Grid workflows or concentrate on business process management. In this paper we present a survey of available workflow annotation and composition approaches in all of these areas. We additionally categorize and compare them and describe future work.

关键词： Surveys

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Mildly context-sensitive dependency languages

Mildly context-sensitive dependency languages

引用

45th Annual Meeting of the Association for Computational Linguistics, ACL 2007

作者： Kuhlmann, Marco Möhl, Mathias Programming Systems Lab. Saarland University Saarbrücken Germany

ISBN: (纸本)9781932432862

Dependency-based representations of natural language syntax require a fine balance between structural flexibility and computational complexity. In previous work, several constraints have been proposed to identify classes of dependency structures that are wellbalanced in this sense;the best-known but also most restrictive of these is projectivity. Most constraints are formulated on fully specified structures, which makes them hard to integrate into models where structures are composed from lexical information. In this paper, we show how two empirically relevant relaxations of projectivity can be lexicalized, and how combining the resulting lexicons with a regular means of syntactic composition gives rise to a hierarchy of mildly context-sensitive dependency languages. © 2007 Association for Computational Linguistics.

关键词： Syntactics

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Impacts of multiprocessor configurations on workloads in bioinformatics

Impacts of multiprocessor configurations on workloads in bio...

引用

19th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD

作者： Wu, Youfeng Breternitz Jr., Mauricio Ying, Victor Programming Systems Lab. Microprocessor Technology Labs. Intel Corporation

ISBN: (纸本)9780769530147

Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with different configurations, and examine the effects of the configurations on the performance of the workloads. Our result indicates that the configurations of the multiprocessor systems have significant impact on the performance and scalability of the workloads. For example, a number of workloads have significantly higher scalability on one of the systems, but poorer absolute performance than on the other system. However, traditional scalability failed to capture the impacts of the system configurations on the workloads. We present insights on what kinds of workloads will run faster on which systems and propose new metrics to capture the impacts of multiple processor configurations on the workloads. These findings not only provide an easy way to compare results running on different systems, but also enable re-configuration of the underlying systems to run specific workloads efficiently. We also show how processor mapping and loop spreading may help map the workoads to the underlining multiprocessor configuration and achieve consistent scalability for these workloads. © 2007 IEEE.

关键词： Bioinformatics

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Enabling scalability and performance in a large scale CMP environment 07

Enabling scalability and performance in a large scale CMP en...

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2007 Eurosys Conference

作者： Saha, Bratin Adl-Tabatabai, Ali-Reza Ghuloum, Anwar Rajagopalan, Mohan Hudson, Richard L. Petersen, Leaf Menon, Vijay Murphy, Brian Shpeisman, Tatiana Sprangle, Eric Rohillah, Anwar Carmean, Doug Fang, Jesse Programming Systems Lab. Intel Corporation Digital Enterprise Group Intel Corporation

ISBN: (纸本)159593636X

Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While existing CMP machines have traditionally been handled in the same way as SMPs, this magnitude of parallelism introduces several fundamental challenges at the architectural level and this, in turn, translates to novel challenges in the design of the software stack for these platforms. This paper presents the "Many Core Run Time" (McRT), a software prototype of an integrated language runtime that was designed to explore configurations of the software stack for enabling performance and scalability on large scale CMP platforms. This paper presents the architecture of McRT and discusses our experiences with the system, including experimental evaluation that lead to several interesting, non-intuitive findings, providing key insights about the structure of the system stack at this scale. A key contribution of this paper is to demonstrate how McRT enables near linear improvements in performance and scalability for desktop workloads such as the popular XviD encoder and a set of RMS (recognition, mining, and synthesis) applications. Another key contribution of this work is its use of McRT to explore non-traditional system configurations such as a light-weight executive in which McRT runs on "bare metal" and replaces the traditional OS. Such configurations are becoming an increasingly attractive alternative to leverage heterogeneous computing uints as seen in today's CPU-GPU configurations. Copyright 2007 ACM.

关键词： Large scale systems

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Modeling semantic web services using UML 2

Modeling semantic web services using UML 2

引用

3rd International Workshop on Model-Driven Enterprise Information systems - MDEIS 2007;In Conjunction with ICEIS 2007

作者： Lautenbacher, Florian Bauer, Bemhard Programming Distributed Systems Lab. Institute of Computer Science University of Augsburg Germany

ISBN: (纸本)9789898111005

The development of web services and especially semantic web services is a tremendous task for people who are not familiar with all language constructs. Especially with the growing mass of several semantic web service approaches a language-independent service development is needed. This gap can be filled by using model-driven software development. Therefore, in this paper we introduce a meta-model for semantic web services and show the benefits of automatic code generation on the basis of a small example.

关键词： Web services

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Thread scheduling for multi-core platforms 11

Thread scheduling for multi-core platforms

引用

11th Workshop on Hot Topics in Operating systems, HotOS 2007

作者： Rajagopalan, Mohan Lewis, Brian T. Anderson, Todd A. Programming Systems Lab Intel Corporation Santa ClaraCA94054 United States

As multi-core processors with tens or hundreds of cores begin to proliferate, system optimization issues once faced only by the high-performance computing (HPC) community will become important to all programmers. However, unlike with HPC, the focus of the multi-core programmer will be on programming productivity and portability as much as performance. We introduce in this paper a novel scheduling framework for multi-core processors that strikes a balance between control over the system and the level of abstraction. Our framework uses high-level information supplied by the user to guide thread scheduling and also, where necessary, gives the programmer fine control over thread placement. © HotOS 2007.

关键词： Scheduling

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Transactional programming in a multi-core environment 07

Transactional programming in a multi-core environment

引用

2007 ACM SIGPLAN Symposium on Principles and Practice of Parallel programming, PPoPP'07

作者： Adl-Tabatabai, Ali-Reza Kozyrakis, Christos Saha, Bratin Programming Systems Lab. Microprocessor Technology Lab. Intel Corporation Computer Systems Lab. Electrical Engineering Department Stanford University

ISBN: (纸本)1595936025

With single thread performance starting to plateau, HW architects have turned to chip level multiprocessing (CMP) to increase processing power. All major microprocessor companies are aggressively shipping multi-core products in the mainstream computing market. Moore's law will largely be used to increase HW thread-level parallelism through higher core counts in a CMP environment. CMPs bring new challenges into the design of the software system stack. In this tutorial, we talk about the shift to multi-core processors and the programming implications. In particular, we focus on transactional programming. Transactions have emerged as a promising alternative to lock-based synchronization that eliminates many of the problems associated with lock-based synchronization. We discuss the design of both hardware and software transactional memory and quantify the tradeoffs between the different design points. We show how to extend the Java and C languages with transactional constructs, and how to integrate transactions with compiler optimizations and the language runtime (e.g., memory manager and garbage collection).

关键词： Computer programming

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