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检索条件"机构=programming Systems Lab"
95 条 记 录,以下是61-70 订阅
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Software transactional memory
Software transactional memory
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IEEE Hot Chips Symposium (HCS)
作者: Bratin Saha Programming Systems Lab Intel Corporation
This article consists of a collection of slides from the author's conference presentation on software transactional memory (STM). Some of the specific topics discussed include: how to translate a language construc... 详细信息
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Transactional memory introduction
Transactional memory introduction
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IEEE Hot Chips Symposium (HCS)
作者: Ali-Reza Adl-Tabatabai Programming Systems Lab Intel Corporation
Presents a collection of slides covering the following topics: Transactional Memory language construct; synchronised HashMap; transactional HashMap; Java; failure recovery; and parallel programming.
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Compositional abstractions for search factories
Compositional abstractions for search factories
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Second International Conference - Multiparadigm programming in Mozart/OZ, MOZ 2004
作者: Tack, Guido Botlan, Didier Le Programming Systems Lab Saarland University Germany
Search is essential for constraint programming. Search engines typically combine several features like state restoration for back-tracking, best solution search, parallelism, or visualization. In current implementatio... 详细信息
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A categorization of collaborative business process modeling techniques
A categorization of collaborative business process modeling ...
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IEEE International Conference on E-Commerce Technology Workshops
作者: S. Roser B. Bauer Programming Distributed Systems Lab Institute of Computer Science University of Augsburg Germany
Business process modeling (BPM) is one of the key factors in defining service-oriented solutions for business collaborations. Like in traditional software engineering there is a need for adaptable methodologies to dev... 详细信息
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POV-Ray parallelization and optimization: An experience report
POV-Ray parallelization and optimization: An experience repo...
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2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05
作者: Yang, Chen Chen, Yongjian Fu, Xiong Lim, Chu-Cheow Ju, Roy KeXue Yuan South Road ZhongGuanCun HaiDian Dist Beijing 100086 China Programming Systems Lab/MTL SC12-323 2200 Mission College Blvd Santa Clara CA 95052-8119 United States
With the industry trend towards multi-core chip, we need to understand the practical issues faced by users who are porting large existing sequential software to a parallel platform. There is much literature on inventi... 详细信息
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A dynamic compilation framework for controlling microprocessor energy and performance  38
A dynamic compilation framework for controlling microprocess...
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MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture
作者: Wu, Qiang Reddi, V.J. Wu, Youfeng Lee, Jin Connors, Dan Brooks, David Martonosi, Margaret Clark, Douglas W. Depts. of Computer Science Electrical Engjneering Princeton University Dept. of Electrical and Computer Engineering U. of Colorado Boulder Programming Systems Lab. Corporate Tech. Group Intel Corporation Division of Engineering and Applied Science Harvard University
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-comp... 详细信息
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Enhanced code density of embedded CISC processors with Echo technology  05
Enhanced code density of embedded CISC processors with Echo ...
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3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and systems Synthesis CODES+ISSS 2005
作者: Wu, Youfeng Breternitz Jr., Mauricio Hum, Herbert Peri, Ramesh Pickett, Jay Programming Systems Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Low Power Microprocessor Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Compiler Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States
Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance... 详细信息
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Lexicalized syntax and topology for non-projective dependency grammar
Lexicalized syntax and topology for non-projective dependenc...
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Proceedings of the Joint Meeting of the 6th Conference on Formal Grammar and the 7th Conference on Mathematics of Language
作者: Duchier, Denys Programming Systems Lab Universität des Saarlandes Saarbrücken Germany
We propose a lexicalized formulation of dependency grammar that addresses both immediate dependence and linear precedence. Our approach distinguishes two orthogonal, yet mutually constraining dependency trees: an ID t... 详细信息
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Lexicalized Syntax and Topology for Non-projective Dependency Grammar
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Electronic Notes in Theoretical Computer Science 2004年 53卷 70-80页
作者: Denys Duchier Programming Systems Lab Universität des Saarlandes Saarbrücken Germany
We propose a lexicalized formulation of dependency grammar that addresses both immediate dependence and linear precedence. Our approach distinguishes two orthogonal, yet mutually constraining dependency trees: an ID t...
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A cost-driven compilation framework for speculative parallelization of sequential programs
A cost-driven compilation framework for speculative parallel...
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Proceedings of the 2004 ACM SIGPLAN Conference on programming Language Design and Implementation (PLDI'04)
作者: Du, Zhao-Hui Yang, Chen Lim, Chu-Cheow Zhao, Qingyu Li, Xiao-Feng Ngai, Tin-Fook Intel China Research Center Intel China Ltd. Beijing China Programming Systems Lab Intel Corporation Santa Clara California United States
The emerging hardware support for thread-level speculation opens new opportunities to parallelize sequential programs beyond the traditional limits. By speculating that many data dependences are unlikely during runtim... 详细信息
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