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IEEE Hot Chips Symposium (HCS)

作者： Bratin Saha Programming Systems Lab Intel Corporation

This article consists of a collection of slides from the author's conference presentation on software transactional memory (STM). Some of the specific topics discussed include: how to translate a language construct via STM, including runtime and compiler support; example of hybrid TM; and the outlook for the future development STM and the applications to be supported.

关键词： Software development programming Runtime Transactional memory Optimization Data structures Memory management

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Transactional memory introduction

Transactional memory introduction

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IEEE Hot Chips Symposium (HCS)

作者： Ali-Reza Adl-Tabatabai Programming Systems Lab Intel Corporation

Presents a collection of slides covering the following topics: Transactional Memory language construct; synchronised HashMap; transactional HashMap; Java; failure recovery; and parallel programming.

关键词： programming Hardware Java Transactional memory Data structures Instruction sets Memory management

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Compositional abstractions for search factories

Compositional abstractions for search factories

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Second International Conference - Multiparadigm programming in Mozart/OZ, MOZ 2004

作者： Tack, Guido Botlan, Didier Le Programming Systems Lab Saarland University Germany

Search is essential for constraint programming. Search engines typically combine several features like state restoration for back-tracking, best solution search, parallelism, or visualization. In current implementations like Mozart, however, these search engines are monolithic and hard-wired to one exploration strategy, severely complicating the implementation of new exploration strategies and preventing their reuse. This paper presents the design of a search factory for Mozart, a program that enables the user to freely combine several orthogonal aspects of search, resulting in a search engine tailored to the user's needs. The abstractions developed here support fully automatic recomputation with last alternative optimization. They present a clean interface, making the implementation of new exploration strategies simple. Conservative extensions of the abstractions are presented that support best solution search and parallel search as orthogonal modules. IOzSeF, the Interactive Oz Search Factory, implements these abstractions and is freely available for download. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Computer programming

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A categorization of collaborative business process modeling techniques

A categorization of collaborative business process modeling ...

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IEEE International Conference on E-Commerce Technology Workshops

作者： S. Roser B. Bauer Programming Distributed Systems Lab Institute of Computer Science University of Augsburg Germany

Business process modeling (BPM) is one of the key factors in defining service-oriented solutions for business collaborations. Like in traditional software engineering there is a need for adaptable methodologies to develop information and communication technology (ICT) systems supporting collaborative business processes. In this work we introduce a categorization for the classification of modeling languages and approaches used to model collaborative business processes. Considering an example, we show how the classification of modeling languages and approaches facilitates the development of methodologies for collaborative business processes.

关键词： Collaboration Standardization Collaborative work Application software Software engineering Collaborative software Service oriented architecture Standards organizations Standards development Computer science

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POV-Ray parallelization and optimization: An experience report

POV-Ray parallelization and optimization: An experience repo...

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2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05

作者： Yang, Chen Chen, Yongjian Fu, Xiong Lim, Chu-Cheow Ju, Roy KeXue Yuan South Road ZhongGuanCun HaiDian Dist Beijing 100086 China Programming Systems Lab/MTL SC12-323 2200 Mission College Blvd Santa Clara CA 95052-8119 United States

ISBN: (纸本)1932415602

With the industry trend towards multi-core chip, we need to understand the practical issues faced by users who are porting large existing sequential software to a parallel platform. There is much literature on inventing, implementing and optimizing parallel algorithms. We study what a user needs in order to come up with an efficient parallel program, starting from a sequential application. We parallelized, debugged and optimized a large, public-domain ray-tracing code (POV-Ray). We built a performance tool to predict parallel POV-Ray's scalability on different platforms. The performance prediction tool and modeling was an important part of the optimization methodology because it guides the user's expectations on the potential benefits of more efforts to identify performance bottlenecks. We describe the steps in our POV-Ray work, and summarize potential relevant research issues. Even for a sequential algorithm which can be "embarrassingly parallelized", there is still much scope for further research to simplify the user's parallelization and optimization efforts.

关键词： Ray tracing

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A dynamic compilation framework for controlling microprocessor energy and performance 38

A dynamic compilation framework for controlling microprocess...

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MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Wu, Qiang Reddi, V.J. Wu, Youfeng Lee, Jin Connors, Dan Brooks, David Martonosi, Margaret Clark, Douglas W. Depts. of Computer Science Electrical Engjneering Princeton University Dept. of Electrical and Computer Engineering U. of Colorado Boulder Programming Systems Lab. Corporate Tech. Group Intel Corporation Division of Engineering and Applied Science Harvard University

ISBN: (纸本)0769524400

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrialstrength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3X-5X better than static voltage scaling, and is more than 2X (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control. © 2005 IEEE.

关键词： Microprocessor chips

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Enhanced code density of embedded CISC processors with Echo technology 05

Enhanced code density of embedded CISC processors with Echo ...

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3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and systems Synthesis CODES+ISSS 2005

作者： Wu, Youfeng Breternitz Jr., Mauricio Hum, Herbert Peri, Ramesh Pickett, Jay Programming Systems Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Low Power Microprocessor Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Compiler Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States

ISBN: (纸本)1595931619

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty. Copyright 2005 ACM.

关键词： Microprocessor chips

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Lexicalized syntax and topology for non-projective dependency grammar

Lexicalized syntax and topology for non-projective dependenc...

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Proceedings of the Joint Meeting of the 6th Conference on Formal Grammar and the 7th Conference on Mathematics of Language

作者： Duchier, Denys Programming Systems Lab Universität des Saarlandes Saarbrücken Germany

We propose a lexicalized formulation of dependency grammar that addresses both immediate dependence and linear precedence. Our approach distinguishes two orthogonal, yet mutually constraining dependency trees: an ID tree of syntactic dependencies and a LP tree of topological dependencies. The ID tree is non-ordered, non-projective and its edges are labeled by grammatical functions. The LP tree is ordered and projective and expresses licensed linearizations;its edges are labeled by topological fields. The LP tree can be regarded as deriving from the ID tree through a process of emancipation controlled by lexicalized constraints and principles. In the present article, we formalize valid ID/LP analyses and show how they can be characterized as the solutions of a constraint satisfaction problem. The latter can be solved by constraint programming and forms the basis of our implementation. © 2004 Published by Elsevier Science B.V.

关键词： Context free grammars

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Lexicalized Syntax and Topology for Non-projective Dependency Grammar

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Electronic Notes in Theoretical Computer Science 2004年 53卷 70-80页

作者： Denys Duchier Programming Systems Lab Universität des Saarlandes Saarbrücken Germany

We propose a lexicalized formulation of dependency grammar that addresses both immediate dependence and linear precedence. Our approach distinguishes two orthogonal, yet mutually constraining dependency trees: an ID tree of syntactic dependencies and a LP tree of topological dependencies. The ID tree is non-ordered, non-projective and its edges are labeled by grammatical functions. The LP tree is ordered and projective and expresses licensed linearizations; its edges are labeled by topological fields. The LP tree can be regarded as deriving from the ID tree through a process of emancipation controlled by lexicalized constraints and principles. In the present article, we formalize valid ID/LP analyses and show how they can be characterized as the solutions of a constraint satisfaction problem. The latter can be solved by constraint programming and forms the basis of our implementation.

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A cost-driven compilation framework for speculative parallelization of sequential programs

A cost-driven compilation framework for speculative parallel...

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Proceedings of the 2004 ACM SIGPLAN Conference on programming Language Design and Implementation (PLDI'04)

作者： Du, Zhao-Hui Yang, Chen Lim, Chu-Cheow Zhao, Qingyu Li, Xiao-Feng Ngai, Tin-Fook Intel China Research Center Intel China Ltd. Beijing China Programming Systems Lab Intel Corporation Santa Clara California United States

The emerging hardware support for thread-level speculation opens new opportunities to parallelize sequential programs beyond the traditional limits. By speculating that many data dependences are unlikely during runtime, consecutive iterations of a sequential loop can be executed speculatively in parallel. Runtime parallelism is obtained when the speculation is correct. To take full advantage of this new execution model, a program needs to be programmed or compiled in such a way that it exhibits high degree of speculative thread-level parallelism. We propose a comprehensive cost-driven compilation framework to perform speculative parallelization. Based on a misspeculation cost model, the compiler aggressively transforms loops into optimal speculative parallel loops and selects only those loops whose speculative parallel execution is likely to improve program performance. The framework also supports and uses enabling techniques such as loop unrolling, software value prediction and dependence profiling to expose more speculative parallelism. The proposed framework was implemented on the ORC compiler. Our evaluation showed that the cost-driven speculative parallelization was effective. Our compiler was able to generate good speculative parallel loops in ten Spec2000Int benchmarks, which currently achieve an average 8% speedup. We anticipate an average 15.6% speedup when all enabling techniques are in place.

关键词： Parallel processing systems

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