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International Conference on Pattern Recognition

作者： C. Rodriguez J. Muguerza M. Navarro A. Zarate J.I. Martin J.M. Perez Computer Architecture and Technology Department University of Basque Country (UPV-EHU) Donostia San Sebastian Spain

A classifier for an automatic system that recognizes multifont typewritten digits, often broken and blurred, in forms is presented. The classification, which is based on the utilization of a global feature, is applied in two phases. Firstly, a minimum distance method (1-NN) is applied in a multifont classifier to provide a global classification of the patterns in a form. A problem associated to multifont classifiers is the interference among classes in different fonts. An interesting aspect of this particular application is that it is highly probable that a form includes just one font. Then, in the second phase, a specialized classifier, oriented to one-form, uses the patterns in the form previously classified to validate, or reject and reclassify them, on the basis of the mean distance to the predefined classes. This specialized classifier affords significant improvement in performance. A classification accuracy rate of 99.42% has been achieved.

关键词： Optical character recognition software Application software Handwriting recognition Prototypes Feature extraction computer architecture Electronic mail Interference Humans Character recognition

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Segmentation of low-quality typewritten digits

Segmentation of low-quality typewritten digits

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International Conference on Pattern Recognition

作者： C. Rodriguez J. Muguerza M. Navarro A. Zarate J.I. Martin J.M. Perez Computer Architecture and Technology Department University of Basque Country (UPV-EHU) Donostia San Sebastian Spain

This work addresses the segmentation of numeric fields in forms presenting blurring, breaks and touching in digits. In an OCR system, the segmentation phase plays a determinant role in the global accuracy of the system. Segmentation is basically addressed from two approaches: (a) as an isolated phase in the OCR process, and (b) as interacting with the recognition of the segmented item. In this work, we have considered the first one in order to develop a robust new cost function combining vertical projection, Tsujimoto metric (1991) and background information. Unlike other techniques reported in the literature, ours obtains a near-optimum number of break points in fields containing broken, blurred and touching characters, leading to high accuracy in the global OCR system. Our experiments with a sample including about 11283 numeric fields in 144 forms (more than 50000 digits of that kind) show that 99.74% of fields have been correctly segmented. The new cost function only made 50 errors.

关键词： Optical character recognition software Image segmentation Cost function Read only memory computer architecture Electronic mail Character recognition Feature extraction Image quality Text recognition

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Special ATPG to correlate test patterns for low-overhead mixed-mode BIST

Special ATPG to correlate test patterns for low-overhead mix...

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Asian Test Symposium (ATS)

作者： M. Karkala N.A. Touba H.-J. Wunderlich Computer Engineering Research Center Department of Electrical and Computer Engineering University of Technology Austin TX USA Computer Architecture Laboratory University of Stuttgart Stuttgart Germany

In mixed-mode BIST, deterministic test patterns are generated with on-chip hardware to detect the random-pattern-resistant (r.p.r.) faults that are missed by the pseudo-random patterns. While previous work in mixed-mode BIST has focused on developing hardware schemes for more efficiently encoding a given set of deterministic patterns (generated by a conventional ATPG procedure), the approach taken in this paper is to improve the encoding efficiency (and hence reduce hardware overhead) by specially selecting a set of deterministic test patterns for the r.p.r. faults that can be efficiently encoded. A special ATPG procedure is described for finding test patterns for the r.p.r. faults that are correlated (have the same logic value) in many bit positions. Such test patterns can be efficiently encoded with one of the many "bit-fixing" schemes that have been described in the literature. Results are shown for different bit-fixing schemes which indicate dramatic reductions in BIST overhead can be achieved by using the proposed ATPG procedure to select which test patterns to encode.

关键词： Automatic test pattern generation Built-in self-test Circuit testing Test pattern generators Circuit faults Read only memory Encoding Automatic testing Fault detection Character generation

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Pipelined Hogenauer CIC filters using field-programmable logic and residue number system

Pipelined Hogenauer CIC filters using field-programmable log...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： A. Garcia U. Meyer-Baese F. Taylor Department of Electronics and Computer Technology University of Granada Granada Spain High Speed Digital Architecture Laboratory University of Florida Gainesville USA

Field-programmable logic (FPL) is on the verge of revolutionizing digital signal processing (DSP) in the manner that programmable DSP microprocessors did nearly two decades ago. While FPL densities and performance have steadily improved to the point where some DSP solutions can be integrated into a single FPL chip, they still have limited use in high-precision high-bandwidth applications. It is shown that in such cases, the residue number system (RNS) can be an enabling technology. The design of a high-decimation rate digital filter is presented which demonstrates the RNS-FPL synergy.

关键词： Logic Digital signal processing Digital signal processing chips Arithmetic Finite impulse response filter Electronic mail Microprocessors Digital filters Pipeline processing Bandwidth

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Consequences of port restrictions on testing address decoder faults in two-port memories

Consequences of port restrictions on testing address decoder...

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Asian Test Symposium (ATS)

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department of Electrical Engineering Section of Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only or write-only ports) on the tests; in addition it covers the test strategy for address decoder faults in two-port memories.

关键词： Decoding System testing Read-write memory computer architecture Electronic mail Performance evaluation Random access memory Interference

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The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing

The VEGA moderately parallel MIMD, moderately parallel SIMD,...

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International Symposium on Parallel Processing

作者： M. Taveniku A. Ahlander M. Jonsson B. Svensson Ericsson Microwave Systems AB Molndal Sweden Department of Computer Engineering Chalmers University of Technology Gothenburg Sweden Centre for Computer Systems Architecture Halmstad University Halmstad Sweden

In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose "array signal processing" architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance.

关键词： computer architecture Radar signal processing Power dissipation Signal processing Scalability Power system interconnection Real time systems computer networks Signal processing algorithms Prototypes

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Consequences of port restrictions on testing two-port memories

Consequences of port restrictions on testing two-port memori...

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IEEE International Test Conference

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department o Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible fault models, the tests for single-port and two-port memories, as well as the test strategy. This paper presents a test strategy for two-port memories and covers the consequences of the port restrictions (read-only or write-only ports).

关键词： Testing Logic arrays Random access memory Read-write memory Frequency conversion Logic devices Low voltage Conductivity Resource description framework

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FACET: PC-parallel architecture for cost-efficient telemetry processing

FACET: PC-parallel architecture for cost-efficient telemetry...

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IEEE Conference on Aerospace

作者： T. El-Ghazawi P. Chalermwat P. Piamsa-nga A. Ozkaya N. Speciale D. Wilson Computer Engineering and Computer Science Florida Institute of Technology Melbourne FL USA Parallel Architecture Laboratory Department of Electrical Engineering and Computer Science George Washington University Washington D.C. DC USA NASA Goddard Space Flight Center Greenbelt MD USA

NASA's Mission to Planet Earth (MTPE) is planning to launch the Earth Observing System (EOS) starting in 1998. The large number of planned remote sensing satellites will bring 500 Gigabytes of information per day. The EOS Data and Information System (EOSDIS) is responsible for ingesting and archiving this data. One important component of the EOSDIS system is the data operation, which involves extracting the packets and reconstructing and archiving the original remotely sensed data products. Due to transmission errors, the way data is sampled from the different sensors encoded, packets typically arrive out of order and perhaps with some of them missing or repeated. Many special hardware solutions have been proposed to solve this real-time problem. In this paper, we demonstrate a commercial off the shelf (COTS) solution. The hardware capitalizes on the progress made in the area of network of workstations (NOW), particularly PC-clusters. The software and algorithm exploit the data characteristics and parallelism in the telemetry stream to make use of load balancing and efficient parallel processing. It is shown that this solution can provide high-performance to cost and programmability.

关键词： Telemetry Earth Observing System Hardware Planets Remote sensing Satellites Information systems Data mining Out of order Workstations

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The Colarado Multistatic FMCW Radar System

The Colarado Multistatic FMCW Radar System

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European Conference on Microwave

作者： P.J.F. Swart J. Schier A.J.C. van Gemund W.F. van der Zwan J.P. Karelse G.L. Reijns P. van Genderen L.P. Ligthart H.T. Steenstra Department of Information Technology and Systems International Research Centre for Telecommunications-Transmission and Radar Delft Netherlands Academy of Sciences of the Czech Republic Inst. of Information Theory and Automation Delft University of Technology Dept. of Information Technology and Systems Mekelweg 4 2628 CD Delft The Netherlands Tel.: +31 15 278 1023 Fax: +31 15 278 4046. E-mail: schier@utia.cas.cz Computer Architecture and Digital Techniques (CARDIT) Delft University of Technology Dept. of Information Technology and Systems Mekelweg 4 2628 CD Delft The Netherlands Tel.: +31 15 278 1023 Fax: +31 15 278 4046. E-mail: a.vgemund@et.tudelft.nl Department of Information Technology and Systems Computer Architecture and Digital Techniques (CARDIT) Delft University슠of슠Technology Delft Netherlands

A multstatic frequency-modulated continuous wave (FMCW) radar system is under development for use in the control system of autonomous vehicles. The aim of the system, named Colarado, is the 3D location of obstacles in the surrounding environment. In this paper a laboratory prototype system version, the demonstrator, is described and current results are presented.

关键词： Receiving antennas Transmitting antennas Radar signal processing Radar antennas Voltage-controlled oscillators Spatial resolution Radar theory Vehicles Containers Layout

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March U: A test for unlinked memory faults

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IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1997年第3期144卷 155-160页

作者： vandeGoor, AJ Gaydadjiev, GN Department of Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technology Mekelweg 4 Delft 2628 CD The Netherlands

Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts;a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.

关键词： memory tests March tests memory faults fault model simple faults disturb fault

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