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内蒙古自治区呼和浩特市赛罕区大学西街235号 邮编: 010021
作者机构:Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Tsinghua Univ BNRist Beijing 100084 Peoples R China Beijing Jiaotong Univ Sch Elect & Informat Engn Beijing 100044 Peoples R China Arizona State Univ Dept Elect Comp & Energy Engn Tempe AZ 85287 USA Tsinghua Univ Dept Precis Instrument Beijing 100084 Peoples R China Tsinghua Univ Dept Mech Engn Beijing 100084 Peoples R China
出 版 物:《IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS》 (IEEE集成电路与系统的计算机辅助设计汇刊)
年 卷 期:2021年第40卷第11期
页 面:2237-2250页
核心收录:
学科分类:0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)]
基 金:National Key Research and Development Program of China [2018YFB1702500] Beijing Innovation Center for Future Chips, Tsinghua University
主 题:Random access memory Correlation Program processors System-on-chip Training Arrays Writing Convolutional neural network (CNN) processor correlation enhancement data patterns low power SRAM
摘 要:Convolutional neural network (CNN) has been widely deployed in various processors for intelligent visual signal processing. However, the large amount of activations and weights in CNN causes huge power consumption on SRAM access. Data-adaptive SRAM design is a widely studied method to reduce SRAM reading power based on the utilization of data patterns, while current designs only exploit data patterns in a coarse granularity, and have no advantages when faced with randomly distributed weight data. In this article, we propose a hardware-software co-design scheme to reduce SRAM reading power for CNN processing. First, we propose a reconfigurable data-adaptive SRAM architecture with column data segmentation (CDS-RSRAM) to utilize data patterns. Data in one column is partitioned into several segments, and finer-grained data patterns are exploited within each segment for further reading power reduction. Then, a novel training method-minimum segmented neighbor difference (miniSND)-is proposed for enhancing the correlation of weights. MiniSND improves the similarity of weights without classification accuracy degradation, thus weights could benefit from CDS-RSRAM and be read out with less power consumption. Simulation results demonstrate that the co-design scheme saves up to 66%(8b)/89%(2b) power consumption compared with 8T SRAM.