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内蒙古自治区呼和浩特市赛罕区大学西街235号 邮编: 010021
作者机构:Gwangju Inst Sci & Technol Sch Elect Engn & Comp Sci Gwangju 61005 South Korea
出 版 物:《IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS》 (IEEE工业电子学汇刊)
年 卷 期:2021年第68卷第8期
页 面:7567-7576页
核心收录:
学科分类:0808[工学-电气工程] 08[工学] 0804[工学-仪器科学与技术] 0811[工学-控制科学与工程]
基 金:MOTIE MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program [IITP-2020-2018-0-01433]
主 题:Kernel Convolution Quantization (signal) Modulation Neural networks Field programmable gate arrays Application specific integrated circuits Binary weight neural network CMOS image sensor convolution operation incremental delta-sigma analog-to-digital converter
摘 要:A CMOS image sensor (CIS) that can perform on-chip binary convolution is presented. The CIS can greatly reduce memory usage and computational complexity by directly generating a feature map for a binary neural network. The pixel readout of the CIS is performed in the column-parallel fashion using incremental delta-sigma analog-to-digital converters (ADCs). The CIS operates in two different modes: convolution and normal modes. When the column ADC is working in the convolution mode, it works as a first-order delta-sigma ADC and generates convolved images using a binary kernel. In the normal operation mode, the ADC is switched to a second-order delta-sigma ADC with little hardware modification and used to capture high-quality images. To demonstrate the CIS architecture, a 192 x 128-pixel CIS, which occupies an active die area of 14.44 mm(2), is fabricated in a 0.18 mu m standard CMOS process. The performance of the CIS is evaluated through measurements and network simulations. In the normal operation mode, the CIS achieves a read noise of 14.79 e(rms)(-) and a full-well capacity of 6,420 e(-) with a resulting dynamic range of 53 dB. The power consumptions of the CIS are 49.2 and 52.5 mW during the normal and convolution modes, respectively.