Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

作     者：Seifoori, Zeinab Asadi, Hossein Stojilovic, Mirjana 

作者机构：Sharif Univ Technol Dept Comp Engn Tehran *** Iran Ecole Polytech Fed Lausanne EPFL Sch Comp & Commun Sci CH-1015 Lausanne Switzerland 

出 版 物：《IEEE ACCESS》 (IEEE Access)

年 卷 期：2021年第9卷

页      面：115599-115619页

核心收录：

基　　金：cole Polytechnique Fdrale de Lausanne Sharif University of Technology 

主　　题：Field programmable gate arrays Routing Power demand Clustering algorithms Machine learning algorithms Switches Benchmark testing Field-programmable gate arrays static power consumption power gating routing algorithm machine learning 

摘      要：Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA routing resources. In the first group of proposed algorithms, we employ K-means clustering and exploit the utilization pattern of routing resources. In the second group of algorithms, we enhance the power-gating efficiency by minimizing the power overhead introduced by power-gating logic and by taking into account the size of routing multiplexers, which influences the power-gating efficiency. Finally, we enhance and further develop the baseline FPGA routing algorithm to be aware and take advantage of power gating opportunities. The experimental results on Titan benchmark suite and the latest Intel Stratix-IV FPGA architecture in VTR 8.0 show that our approaches achieve an improvement of about 70%, on average, in reducing the FPGA static power consumption over the best power-gating approaches proposed in the previous studies.