OmpSs@FPGA Framework for High Performance FPGA Computing

作     者：Miguel de Haro, Juan Bosch, Jaume Filgueras, Antonio Vidal, Miquel Jimenez-Gonzalez, Daniel Alvarez, Carlos Martorell, Xavier Ayguade, Eduard Labarta, Jesus 

作者机构：Barcelona Supercomp Ctr BSC Barcelona 08034 Catalonia Spain Univ Politecn Catalunya UPC Barcelona 08034 Catalonia Spain 

出 版 物：《IEEE TRANSACTIONS ON COMPUTERS》 (IEEE计算机汇刊)

年 卷 期：2021年第70卷第12期

页      面：2029-2042页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：European Union's Horizon 2020 Research and Innovation Programme through EuroEXA project Spanish Government [PID2019-107255GB, SEV2015-0493, BES-2016-078046] Generalitat de Catalunya [2017-SGR-1414, 2017-SGR-1328] 

主　　题：Field programmable gate arrays Task analysis Hardware Runtime Programming Tools Random access memory FPGA reconfigurable hardware parallel architectures task-based programming models high-level synthesis 

摘      要：This article presents the new features of the OmpSs@FPGA framework. OmpSs is a data-flow programming model that supports task nesting and dependencies to target asynchronous parallelism and heterogeneity. OmpSs@FPGA is the extension of the programming model addressed specifically to FPGAs. OmpSs environment is built on top of Mercurium source to source compiler and Nanos++ runtime system. To address FPGA specifics Mercurium compiler implements several FPGA related features as local variable caching, wide memory accesses or accelerator replication. In addition, part of the Nanos++ runtime has been ported to hardware. Driven by the compiler this new hardware runtime adds new features to FPGA codes, such as task creation and dependence management, providing both performance increases and ease of programming. To demonstrate these new capabilities, different high performance benchmarks have been evaluated over different FPGA platforms using the OmpSs programming model. The results demonstrate that programs that use the OmpSs programming model achieve very competitive performance with low to moderate porting effort compared to other FPGA implementations.