A Resource Efficient Software-Hardware Co-Design of Lattice-Based Homomorphic Encryption Scheme on the FPGA

作     者：Paul, Bikram Yadav, Tarun Kumar Singh, Balbir Krishnaswamy, Srinivasan Trivedi, Gaurav 

作者机构：Indian Inst Technol Guwahati Dept Elect & Elect Engn Gauhati 781039 Assam India 

出 版 物：《IEEE TRANSACTIONS ON COMPUTERS》 (IEEE Trans Comput)

年 卷 期：2023年第72卷第5期

页      面：1247-1260页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Visvesvaraya PhD Scheme for Electronics and IT Ministry of Electronics and Information Technology Ministry of Education, Youth and Sports, Czech Republic Department of Science and Technology, India 

主　　题：Homomorphic encryption Field programmable gate arrays Internet of Things Hardware acceleration Computer architecture Lattices IP networks Partially homomorphic encryption hidden subspace membership problem learning with errors FPGA system-on-chip low power device 

摘      要：Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this article, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-System on Chip (ARM-SoC) and an field programmable gate array (FPGA). This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog hardware description language on multiple FPGA platforms. The proposed lightweight scheme is 52.71x more resource-efficient than the pipelined BGV RLWE-based method. It exhibits 1.43x and 1.29x better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.