An Efficient Algorithm-Hardware Co-Design for Radar-Based Fall Detection With Multi-Branch Convolutions

作     者：Ou, Zixuan Yu, Bing Ye, Wenbin 

作者机构：Shenzhen University College of Electronics and Information Engineering Shenzhen 518060 China 

出 版 物：《IEEE Transactions on Circuits and Systems I: Regular Papers》 (IEEE Trans. Circuits Syst. Regul. Pap.)

年 卷 期：2023年第70卷第4期

页      面：1613-1624页

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0835[工学-软件工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：algorithm-hardware co-design convolutional neural network Fall detection low cost low power radar signal processing 

摘      要：In this paper, we propose an efficient algorithm-hardware co-design framework to realize radar-based fall detection with limited resources. We first design a compact neural network model named MB-Net with multi-branch convolutions for feature extraction of radar time series data combined with multi-scale wavelet transform. After that, an FPGA-based neural network (NN) accelerator tailored for the proposed network is designed. The proposed NN accelerator replaces the general multipliers with non-exact multipliers to reduce the hardware cost. For the multi-branch convolution layer, a novel layer computing sequence is introduced to improve the efficiency of the processing element (PE) array and reduce the memory footprint. In addition, the average pooling operation in the proposed network is folded into the quantization factors to reduce hardware cost. The experimental findings show that the MB-Net can maintain competitive performance in comparison to state-of-the-art methods while the hardware cost is significantly lower. The proposed network model is implemented in Zynq ZC702 board using only 3615 LUTs, 1843 FFs, 11.5 BRAMs, and 8 DSPs with 0.234 W power consumption. Through algorithm and hardware co-optimization, the fall detection accelerator can achieve 95% PE efficiency and takes 0.346 ms latency for a radar sample interference with only 80.96 uJ energy consumption. © 2004-2012 IEEE.