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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Park, Sunyoung Byun, Wooseok Je, Minkyu Kim, Ji-Hoon Ewha Womans Univ Dept Elect & Elect Engn Seoul South Korea Ewha Womans Univ Grad Program Smart Factory Seoul South Korea SAPEON Korea Inc Seongnam South Korea Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9798350330991;9798350331004

Recent advancements in brain-computer interface (BCI) technology for steady-state visual evoked potential (SSVEP)-based target identification have shifted from traditional linear algebra (LA) techniques to more sophisticated neural network (NN) approaches, driven by their increased accuracy and consistent performance across different subjects. However, adopting NN-based algorithms has introduced complexities in wearable BCI systems, mainly due to their extensive parameter sets that demand significant memory capacity. Moreover, the computational intensity of these models requires reevaluating hardware architectures. Additionally, the advent of Transformerbased models has further advanced the state of the art, providing even higher accuracy and reduced variability in cross-subject performance, placing greater demands on hardware resources. This paper provides an overview of recent algorithmic progress in SSVEP-based target identification. Also, it proposes considerations for the hardware architecture needed to efficiently support the computation of cutting-edge Transformer-based models in wearable BCIs from the perspective of algorithm-hardware codesign.

关键词： Brain-computer interface (BCI) transformer neural network algorithm-hardware co-design domain-specific architecture

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coMN: algorithm-hardware co-design Platform for Nonvolatile Memory-Based convolutional Neural Network Accelerators

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IEEE TRANSACTIONS ON coMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第7期43卷 2043-2056页

作者： Han, Lixia Pan, Renjie Zhou, Zheng Lu, Hairuo Chen, Yiyang Yang, Haozhang Huang, Peng Sun, Guangyu Liu, Xiaoyan Kang, Jinfeng Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China Peking Univ Sch Software & Microelect Beijing 102600 Peoples R China

computing in memory (CIM) convolutional neural network (CNN) accelerators based on nonvolatile memory (NVM) show great potential to improve energy efficiency and throughput, while the multiple design levels and huge design space of CIM-based CNN acceleration system make cross-level co-design methodology and platforms extremely desired. In this work, an algorithm-hardware co-design platform coMN with the graphic user interface is proposed for designers to fast verify and further optimize the designments. In the platform: 1) a mapper is developed to automatically map CNN models to CIM chips through optimizing pipeline, weight transformation, partition, and placement;2) accuracy evaluator and performance evaluator are built to jointly estimate accuracy, energy, latency, and area overheads considering the design dependencies across multiple levels;3) algorithm adapter is exploited to retrain CNN weights for higher-hardware accuracy within limited energy budget through nonidealities aware training and energy aware training;and 4) hardware optimizer is developed to search hardware microarchitecture and circuit design space in the early design stage. We conduct several case studies to verify the effectiveness of the coMN platform. Results indicate that coMN platform can enable algorithm- hardware mapping, hardware-aware algorithm adaption, hardware configuration exploration, and overall algorithm-hardware co-design efficiently. The coMN platform can be accessed online at https://101.42.97.22:8081/*** with username "tcad" and password "comnuser."

关键词： hardware Integrated circuit modeling Performance evaluation Pipelines convolutional neural networks Optimization Nonvolatile memory algorithm-hardware co-design computing in memory (CIM) convolution neural network design space exploration

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High Throughput FPGA-Based Object Detection via algorithm-hardware co-design

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ACM TRANSACTIONS ON REcoNFIGURABLE TECHNOLOGY AND SYSTEMS 2024年第1期17卷 1-20页

作者： Anupreetham, Anupreetham Ibrahim, Mohamed Hall, Mathew Boutros, Andrew Kuzhively, Ajay Mohanty, Abinash Nurvitadhi, Eriko Betz, Vaughn Cao, Yu Seo, Jae-Sun Arizona State Univ Tempe AZ 85287 USA Univ Toronto Toronto ON Canada Intel Corp Santa Clara CA USA Vector Inst AI Toronto ON Canada

Object detection and classification is a key task in many computer vision applications such as smart surveillance and autonomous vehicles. Recent advances in deep learning have significantly improved the quality of results achieved by these systems, making them more accurate and reliable in complex environments. Modern object detection systems make use of lightweight convolutional neural networks (CNNs) for feature extraction, coupled with single-shot multi-box detectors (SSDs) that generate bounding boxes around the identified objects along with their classification confidence scores. Subsequently, a non-maximum suppression (NMS) module removes any redundant detection boxes from the final output. Typical NMS algorithms must wait for all box predictions to be generated by the SSD-based feature extractor before processing them. This sequential dependency between box predictions and NMS results in a significant latency overhead and degrades the overall system throughput, even if a high-performance CNN accelerator is used for the SSD feature extraction component. In this paper, we present a novel pipelined NMS algorithm that eliminates this sequential dependency and associated NMS latency overhead. We then use our novel NMS algorithm to implement an end-to-end fully pipelined FPGA system for low-latency SSD-MobileNet-V1 object detection. Our system, implemented on an Intel Stratix 10 FPGA, runs at 400 MHz and achieves a throughput of 2,167 frames per second with an end-to-end batch-1 latency of 2.13 ms. Our system achieves 5.3x higher throughput and 5x lower latency compared to the best prior FPGA-based solution with comparable accuracy.

关键词： FPGA accelerator object detection algorithm-hardware co-design neural networks

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Advances in Wearable Brain-computer Interfaces From an algorithm-hardware co-design Perspective

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第7期69卷 3071-3077页

作者： Byun, Wooseok Je, Minkyu Kim, Ji-Hoon SAPEON Korea Architecture Team Seongnam 13486 South Korea Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea Ewha Womans Univ Dept Elect & Elect Engn Smart Factory Multidisciplinary Program Seoul 03760 South Korea

Brain-computer interface (BCI), a communication technology between brain and computer developed for a long time since the 1970s, can be incorporated into wearable devices by developing powerful signal processing algorithms and semiconductor technologies. For a satisfactory user experience based on BCI, high information transfer rate and low power consumption should be considered together without losing accuracy. Although many existing BCI algorithms have been mainly focused solely on the accuracy, their deployment on wearable devices is not straightforward due to the limited hardware resources and computational capabilities. This tutorial summarizes recent advances in wearable BCI algorithms and hardware implementations from an algorithm-hardware co-design perspective and discusses future directions.

关键词： Signal processing algorithms Partitioning algorithms hardware Wearable computers Recording Visualization Signal processing Brain-computer interface (BCI) algorithm-hardware co-design domain-specific architecture deep learning accelerator linear algebra accelerator

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An Efficient algorithm-hardware co-design for Radar-Based Fall Detection With Multi-Branch convolutions

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第4期70卷 1613-1624页

作者： Ou, Zixuan Yu, Bing Ye, Wenbin Shenzhen Univ Coll Elect & Informat Engn Shenzhen 518060 Peoples R China

In this paper, we propose an efficient algorithm-hardware co-design framework to realize radar-based fall detection with limited resources. We first design a compact neural network model named MB-Net with multi-branch convolutions for feature extraction of radar time series data combined with multi-scale wavelet transform. After that, an FPGA-based neural network (NN) accelerator tailored for the proposed network is designed. The proposed NN accelerator replaces the general multipliers with non-exact multipliers to reduce the hardware cost. For the multi-branch convolution layer, a novel layer computing sequence is introduced to improve the efficiency of the processing element (PE) array and reduce the memory footprint. In addition, the average pooling operation in the proposed network is folded into the quantization factors to reduce hardware cost. The experimental findings show that the MB-Net can maintain competitive performance in comparison to state-of-the-art methods while the hardware cost is significantly lower. The proposed network model is implemented in Zynq ZC702 board using only 3615 LUTs, 1843 FFs, 11.5 BRAMs, and 8 DSPs with 0.234 W power consumption. Through algorithm and hardware co-optimization, the fall detection accelerator can achieve 95 $\%$ PE efficiency and takes 0.346 ms latency for a radar sample interference with only 80.96 uJ energy consumption.

关键词： Fall detection convolutional neural network radar signal processing algorithm-hardware co-design low power low cost

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ASBNN: Acceleration of Bayesian convolutional Neural Networks by algorithm-hardware co-design 32

ASBNN: Acceleration of Bayesian Convolutional Neural Network...

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32nd IEEE International conference on Application-specific Systems, Architectures and Processors (ASAP)

作者： Fujiwara, Yoshiki Takamaeda-Yamazaki, Shinya Univ Tokyo Bunkyo Ku Tokyo 1138656 Japan

ISBN: (纸本)9781665427012

Bayesian convolutional Neural Networks (BCNNs) have been proposed to address the problem of model uncertainty in conventional neural networks. By treating weights as distributions rather than deterministic values, BCNNs mitigate the problem of overfitting, training with a small amount of data, and uncertainty evaluations. However, computing the distributions of BCNN outputs is time- and energy-consuming because it requires computing multiple forward passes. To address this computational problem, we propose a novel algorithm-hardware co-design approach with an approximation algorithm and hardware support for the rapid computation of BCNN. Our observations of the absolute number of each layer's input and the input difference among multiple forward passes show that most of these values are significantly small compared with other large values. Our algorithm treats these small values as zero and makes them sparser. The extracted sparsity allows us to skip most multiplications. As a result, it achieves a computation reduction of 81.1 % in classification tasks and 77.7 % in regression tasks. Additionally, to support the algorithm-level approximation on hardware, we propose a novel dataflow that is specialized for our algorithm, and develop a new accelerator architecture, accelerator for sparse Bayesian Neural Networks (ASBNN), that can handle sparsity extracted by the algorithm. Our evaluation demonstrates that the ASBNN successfully exploits the algorithmic computation reduction to improve the computation time by 3.3 x and energy efficiency by 3.7x compared with the naive implementation of dense BCNN accelerators.

关键词： Bayesian Neural Network Deep Learning Accelerator algorithm-hardware co-design

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BDLUT: Blind image denoising with hardware-optimized look-up tables

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JOURNAL OF THE SOCIETY FOR INFORMATION DISPLAY 2025年

作者： Li, Boyu Ai, Zhilin Jiang, Baizhou Huang, Binxiao Li, Jason Chun Lok Liu, Jie Tu, Zhengyuan Wang, Guoyu Yu, Daihai Wong, Ngai Univ Hong Kong Dept Elect & Elect Engn Pok Fu Lam Hong Kong 99077 Peoples R China TCL Corp Res HK Co Ltd Pak Shek Kok Hong Kong Peoples R China

Denoising sensor-captured images on edge display devices remains challenging due to deep neural networks' (DNNs) high computational overhead and synthetic noise training limitations. This work proposes BDLUT(-D), a novel blind denoising method combining optimized lookup tables (LUTs) with hardware-centric design. While BDLUT describes the LUT-based network architecture, BDLUT-D represents BDLUT trained with a specialized noise degradation model. designed for edge deployment, BDLUT(-D) eliminates neural processing units (NPUs) and functions as a standalone ASIC IP solution. Experimental results demonstrate BDLUT-D achieves up to 2.42 dB improvement over state-of-the-art LUT methods on mixed-noise-intensity benchmarks, requiring only 66 KB storage. FPGA implementation shows over 10x$$ \times $$ reduction in logic resources, 75% less storage compared to DNN accelerators, while achieving 57% faster processing than traditional bilateral filtering methods. These optimizations enable practical integration into edge scenarios like low-cost webcam enhancement and real-time 4 K-to-4 K denoising without compromising resolution or latency. By enhancing silicon efficiency and removing external accelerator dependencies, BDLUT(-D) establishes a new standard for practical edge imaging denoising. Implementation is available at .

关键词： algorithm-hardware co-design blind denoising lookup table

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OFQ-LLM: Outlier-Flexing Quantization for Efficient Low-Bit Large Language Model Acceleration

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Wang, Gang Cai, Siqi Li, Wenjie Lyu, Dongxu He, Guanghui Shanghai Jiao Tong Univ Sch Integrated Circuits State Key Lab MicroNano Engn Sci Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ Sch Comp Sci Shanghai 200240 Peoples R China

Large Language Models (LLMs) have achieved significant success in various Natural Language Processing (NLP) tasks, becoming essential to modern intelligent computing. Their large memory footprint and high computational cost hinder efficient deployment. Post-Training Quantization (PTQ) is a promising technique to alleviate this issue and accelerate LLM inference. However, the presence of outliers impedes the advancement of LLM quantization to lower bit levels. In this paper, we introduce OFQ-LLM, an algorithm-hardware co-design solution that adopts outlier-flexing quantization to efficiently accelerate LLM at low-bit levels. The key insight of OFQ-LLM is that normal data can be efficiently quantized in a slightly reduced data encoding space, while the rest encoding space can be used for flexible outlier values. During quantization, we use rescale-based clipping (RBC) to optimize accuracy for normal data and group outlier clustering (GOC) to flexibly represent outlier values. At the hardware level, we introduce a memory-aligned outlier-flexing encoding scheme to encode activations and weights in LLMs at a low bit level. The outlier-normal mixed hardware architecture is devised to leverage the encoding scheme and accelerate LLMs with high speed and high energy efficiency. Our experiments show that OFQ-LLM achieves better accuracy compared to state-of-the-art (SOTA) low-bit LLM PTQ works. OFQ-LLM-based accelerator surpasses the SOTA outlier-aware accelerators by up to 2.69x core energy efficiency, up to 3.83x speed up and 2.44x energy reduction in LLM prefilling phase, and up to 2.01x speed up and 2.88x energy reduction in LLM decoding phase, with superior accuracy.

关键词： Quantization (signal) Encoding Accuracy Transformers Decoding Large language models computational modeling Memory management Energy efficiency Training post-training quantization algorithm-hardware co-design outlier efficient acceleration

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M²-ViT: Accelerating Hybrid Vision Transformers With Two-Level Mixed Quantization

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年第5期33卷 1492-1496页

作者： Liang, Yanbiao Shi, Huihong Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

Although vision transformers (ViTs) have achieved significant success, their intensive computations and substantial memory overheads challenge their deployment on edge devices. To address this, efficient ViTs have emerged, typically featuring convolution-transformer hybrid architectures to enhance both accuracy and hardware efficiency. While prior work has explored quantization for efficient ViTs to marry the hardware efficiency of efficient hybrid ViT architectures and quantization, it focuses on uniform quantization and overlooks the potential advantages of mixed quantization. Meanwhile, although several works have studied mixed quantization for standard ViTs, they are not directly applicable to hybrid ViTs due to their distinct algorithmic and hardware characteristics. To bridge this gap, we present M-2-ViT to accelerate convolution-transformer hybrid efficient ViTs with two-level mixed quantization (M(2)Q). Specifically, we introduce a hardware-friendly M(2)Q strategy, characterized by both mixed quantization precision and mixed quantization schemes uniform and power-of-two (PoT), to exploit the architectural properties of efficient ViTs. We further build a dedicated accelerator with heterogeneous computing engines to transform algorithmic benefits into real hardware improvements. The experimental results validate our effectiveness, showcasing an average of 80% energy-delay product (EDP) saving with comparable quantization accuracy compared to the prior work. codes are available at https://***/lybbill/M2ViT.

关键词： Quantization (signal) hardware computational efficiency Accuracy computer architecture Standards Transformers Parallel processing Engines convolutional codes algorithm-hardware co-design efficient vision transformers (ViTs) hardware acceleration mixed quantization ViT

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An Efficient Window-Based Vision Transformer Accelerator via Mixed-Granularity Sparsity

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Dong, Qiwei Zhang, Siyu Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

Vision Transformers (ViTs) have achieved excellent performance on various computer vision tasks, while their high computation and memory costs pose challenges for practical deployment. To address this issue, token-level pruning is used as an effective method to compress ViTs, discarding unimportant image tokens that contribute little to predictions. However, directly applying unstructured token pruning to window-based ViTs damages their regular feature map structure, resulting in load imbalance when deployed on mobile devices. In this work, we propose an efficient algorithm-hardware co-optimized framework to accelerate window-based ViTs via adaptive Mixed-Granularity Sparsity (MGS). At the algorithm level, a hardware-friendly MGS algorithm is developed by integrating the inherent sparsity, global window pruning, and local N:M token pruning to balance model accuracy and its computational complexity. At the hardware level, we present a dedicated accelerator equipped with a sparse computing core and two lightweight auxiliary processing units to execute window-based calculations efficiently using MGS. Additionally, we devise a dynamic pipeline interleaving dataflow to achieve on-chip layer fusion, which reduces the processing latency and maximizes data reuse. Experimental results demonstrate that, with similar computational complexity, our highly structured MGS algorithm can achieve comparable or even better accuracy than previous compression methods. Moreover, compared to existing FPGA-based accelerators for Transformers, our design can achieve 1.80 similar to 6.52x and 1.16 similar to 12.05x improvements in terms of throughput and energy efficiency, respectively.

关键词： algorithm-hardware co-design vision transformer pruning field-programmable gate array (FPGA) algorithm-hardware co-design vision transformer pruning field-programmable gate array (FPGA)

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