High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator for Image Processing and Neural Networks

作     者：Kaushik, Nandit Srinivasu, B. 

作者机构：Indian Inst Technol Mandi Sch Comp & Elect Engn Mandi 175005 India 

出 版 物：《IEEE TRANSACTIONS ON NANOTECHNOLOGY》 (IEEE Trans. Nanotechnol.)

年 卷 期：2024年第23卷

页      面：748-757页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0702[理学-物理学] 

主　　题：Memristors Circuits Logic Image processing Voltage Topology Neural networks Adders Switches Network topology IMPLY MAGIC subtractor memristor adder in-memory computing comparator 

摘      要：In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67x with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43x, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93x faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.