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内蒙古自治区呼和浩特市赛罕区大学西街235号 邮编: 010021
作者机构:Analog Devices Inc I-70021 Milan Italy Politecn Torino DET I-10129 Turin Italy Synopsys P-2740267 Lisbon Portugal Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Brescia Dept Informat Engn I-25123 Brescia Italy
出 版 物:《IEEE ACCESS》 (IEEE Access)
年 卷 期:2025年第13卷
页 面:6594-6605页
核心收录:
主 题:Clocks Calibration Capacitance System-on-chip Resistance Prototypes Impedance Field programmable gate arrays Discharges (electric) Codes D/A converter (DAC) relaxation D/A converter (ReDAC) ultra-low area digital-based ultra-low power ultra-low voltage Internet of Things (IoT) biosensors
摘 要:The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030 mu m(2) and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18dB-SFDR, a 65.59dB-THD and a 56.09dB SINAD, resulting in 9.02ENOB, with a power dissipation of just 3.3 mu W, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (FOMA) of 166dB (175dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800 mu m(2) and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81dB-SFDR, a 77.52dB-THD and a 65.82dB-SINAD (10.64ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOMA) of 172dB (178dB).