Silicon photonics convolution accelerator based on coherent chips with sub-1 pJ/MAC power consumption

作     者：YING ZHU LU XU XIN HUA KAILAI LIU YIFAN LIU MING LUO JIA LIU ZIYUE DANG YE LIU MIN LIU HONGGUANG ZHANG DAIGAO CHEN LEI WANG XI XIAO SHAOHUA YU YING ZHU;LU XU;XIN HUA;KAILAI LIU;YIFAN LIU;MING LUO;JIA LIU;ZIYUE DANG;YE LIU;MIN LIU;HONGGUANG ZHANG;DAIGAO CHEN;LEI WANG;XI XIAO;SHAOHUA YU

作者机构：National Information Optoelectronic Innovation CenterChina Information and Communication Technologies Group Corporation(CICT)Wuhan 430074China State Key Laboratory of Optical Communication Technologies and NetworksChina Information and Communication Technologies Group Corporation(CICT)Wuhan 430074China Peng Cheng LaboratoryShenzhen 518055China 

出 版 物：《Photonics Research》 (光子学研究(英文版))

年 卷 期：2025年第13卷第2期

页      面：497-510页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：National Natural Science Foundation of China(U21A20454  62235017  U23A20356) 

主　　题：silicon photonic integrated circuit artificial intelligence ai coherent chips artificial intelligence convolution accelerator silicon photonic convolution power consumption silicon photonics 

摘      要：Artificial intelligence(AI), owing to its substantial computing demands, necessitates computing hardware that offers both high speed and high power efficiency. A silicon photonic integrated circuit shows promise as a hardware solution due to its attributes, including high power efficiency, low latency, large bandwidth, and complementary metal-oxide-semiconductor(CMOS) compatibility. Here, we propose a silicon photonic convolution accelerator(SiPh-CA) and experimentally realize a prototype with sub-integrated coherent transmit-receive optical sub-assemblies(sub-IC-TROSAs). The prototype, compared to a previous IC-TROSA-based convolution accelerator, achieves almost the same performances of 1.024 TOPS/channel and 96.22% inference accuracy when it processes neural networks for image recognition, using half the numbers of the modulators and the drivers with which over 1/3 chip footprint and 37.01% power consumption are reduced. By incorporating a broadcasting scheme based on splitters and combiners, the approach can efficiently process multiple convolutions in parallel,achieving several tera operations per second. This scalability feature allows the SiPh-CA to process complex AI and high-performance computing tasks.