Incremental design methodology for multimillion-gate FPGAs

作     者：Ma, J Athanas, P Huang, X 

作者机构：Univ New Orleans Dept Elect Engn New Orleans LA 70148 USA Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24060 USA 

出 版 物：《JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS》 (电路、系统与计算机杂志)

年 卷 期：2005年第14卷第5期

页      面：1015-1026页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Virginia Tech Consortium, (DABT-63-99-3-0004) Defense Advanced Research Projects Agency, DARPA Xilinx 

主　　题：incremental techniques placement algorithm JBits APIs design tool core PPGA 

摘      要：This paper presents an FPGA design methodology that can be used to shorten the FPGA design-and-debug cycle, especially as the gate counts increase to multimillions. Core-based incremental placement algorithms, in conjunction with fast interactive routing, axe investigated to reduce the design processing time by distinguishing the changes between design iterations and reprocessing only the changed blocks without affecting the remaining part of the design. When combined with a background refinement thread, the incremental approach offers the instant gratification that designers expect, while preserving the fidelity attained through batch-oriented programs. An integrated FPGA design environment is then developed based on the incremental placer and its background refiner. The results show that the incremental design methodology is in orders of magnitude faster than the competing approaches such as the Xilinx M3 tools without sacrificing too much quality.