A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

作     者：Starzyk, JA Mohn, RP Jing, L 

作者机构：Ohio State Univ Sch Elect Engn & Comp Sci Columbus OH 43701 USA Sarnoff Corp Princeton NJ 08540 USA 

出 版 物：《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS》 (IEEE Trans. Circuits Syst. Regul. Pap.)

年 卷 期：2004年第51卷第1期

页      面：196-200页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

主　　题：CMOS macrocell digital-to-analog converter (DAC) good die yield INL yield SOC integration switching algorithm systematic error reduction 

摘      要：This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-mum six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm(2).