Phase-locked loop used for CDV suppression of MPEG2 signal over ATM network

作     者：Rokugo, Y 

作者机构：NEC Corp Ltd Kawasaki Kanagawa 211 Japan 

出 版 物：《ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS》 (Electron Commun Jpn Part I)

年 卷 期：1998年第81卷第9期

页      面：17-27页

核心收录：

主　　题：ATM digital phase-locked loop picture encoding CDV time stamp 

摘      要：In the transmission of the MPEG2 Transport Stream (MPEG2 TS), the clock information is transferred using the time stamp called the program clock reference (PCR) to synchronize the system clocks between the sending and receiving sides. In this system, a PLL (phase-locked loop) is used to regenerate the system clock from the PCR. Since the PCR is numerical information, new type of PLL is required. Besides, when transmitting MPEG2 signals through the ATM network, the system clock used to generate the PCR and the reference clock of the ATM network become asynchronous. The cell delay variation (CDV) changes the PCR arrival time at the receiving side and produces an ultralow-frequency jitter with a large amplitude when the receiving clocks are regenerated. This jitter cannot be sufficiently eliminated by the conventional second-order PLL model that was used in the stuff synchronous system and in similar schemes. This paper proposes a new type of third-order PLL that efficiently uses the properties of the digital signal processing-type PLL. This paper also evaluates the jitter suppression characteristics of the PLL as compared with those of the second-order PLL. As a result, the proposed PLL obtains strong jitter suppression characteristics without degrading the system gain in a relatively higher-frequency band in which the quality degradation otherwise hinders the regeneration of MPEG2 picture signals. (C) 1998 Scripta Technica.