Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems

作     者：Xiong, Dongliang Huang, Kai Jiang, Xiaowen Yan, Xiaolang 

作者机构：Zhejiang Univ Inst VLSI Design Hangzhou Zhejiang Peoples R China 

出 版 物：《ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION》 (美国计算机协会结构与代码优化汇刊)

年 卷 期：2016年第13卷第4期

页      面：42-42页

核心收录：

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Science Foundation of Zhejiang Province [LY14F020026] 

主　　题：Memory access scheduling hardware complexity memory occupancy dynamic multilevel priority group 

摘      要：Interapplication interference at shared main memory severely degrades performance and increasing DRAM frequency calls for simple memory schedulers. Previous memory schedulers employ a per-application ranking scheme for high system performance or a per-group ranking scheme for low hardware cost, but few provide a balance. We propose DMPS, a memory scheduler based on dynamic multilevel priority. First, DMPS uses memory occupancy to measure interference quantitatively. Second, DMPS groups applications, favors latency-sensitive groups, and dynamically prioritizes applications by employing a per-level ranking scheme. The simulation results show that DMPS has 7.2% better system performance and 22% better fairness over FRFCFS at low hardware complexity and cost.