Field programmable gate array-based Haar classifier for accelerating face detection algorithm

作     者：Gao, C. Lu, S. -L. L. Suh, T. Lim, H. 

作者机构：Broadcom Corp Wireless Connect San Diego CA 92127 USA Intel Corp Oregon Microarchitecture Lab Hillsboro OR 97124 USA Korea Univ Seoul 136701 South Korea 

出 版 物：《IET IMAGE PROCESSING》 (IET Image Proc.)

年 卷 期：2010年第4卷第3期

页      面：184-194页

核心收录：

学科分类：0808[工学-电气工程] 1002[医学-临床医学] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：field programmable gate arrays Logic circuits Image recognition reconfigurable fabric face recognition Logic and switching circuits face detection Computer vision and image processing techniques image classification Haar classifier parallel arithmetic units field programmable gate array Geneseo Initiative pipelined architecture Haar transforms 

摘      要：The authors present a novel approach of using reconfigurable fabric to accelerate a face detection algorithm based on the Haar classifier. With highly pipelined architecture and utilising abundant parallel arithmetic units in FPGA, the authors have achieved real-time performance of face detection with very high detection rate and low false positives. The 1-classifier and 16-classifier realisations in an accelerator provide 10x and 72x speedups, respectively, over the software counterpart. Moreover, the authors , approach is scalable towards the resources available on FPGA and it will gain more momentum as the Geneseo Initiative is introduced in the market. This work also provides an understanding of using the reconfigurable fabric for accelerating non-systolic-based vision algorithms.