A hierarchical design methodology for full-search block matching motion estimation

作     者：Rehan, Mohamed El-Kharashi, M. Watheq Gebali, Fayez 

作者机构：Univ Victoria Dept Elect & Comp Engn Victoria BC V8W 3P6 Canada 

出 版 物：《MULTIDIMENSIONAL SYSTEMS AND SIGNAL PROCESSING》 (多维系统和信号处理)

年 卷 期：2006年第17卷第4期

页      面：327-341页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：full search HDTV H.264 motion estimation MPEG-X processor arrays video compression algorithms video data compression VLSI design 

摘      要：Many useful DSP algorithms have high dimensions and complex logic. Consequently, an efficient implementation of these algorithms on parallel processor arrays must involve a structured design methodology. Full-search block-matching motion estimation is one of those algorithms that can be developed using parallel processor arrays. In this paper, we present a hierarchical design methodology for the full-search block matching motion estimation. Our proposed methodology reduces the complexity of the algorithm into simpler steps and then explores the different possible design options at each step. Input data timing restrictions are taken into consideration as well as buffering requirements. A designer is able to modify system performance by selecting some of the algorithm variables for pipelining or broadcasting. Our proposed design strategy also allows the designer to study time and hardware complexities of computations at each level of the hierarchy. The resultant architecture allows easy modifications to the organization of data buffers and processing elements-their number, datapath pipelining, and complexity-to produce a system whose performance matches the video data sample rate requirements.