Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA

作     者：Kundi, Dur-E-Shahwar Aziz, Arshad 

作者机构：Natl Univ Sci & Technol Dept Elect Engn Islamabad Pakistan 

出 版 物：《MEHRAN UNIVERSITY RESEARCH JOURNAL OF ENGINEERING AND TECHNOLOGY》 

年 卷 期：2015年第34卷第4期

页      面：441-446页

学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 08[工学] 

主　　题：Advance Encryption Standard BRAM Field Programmable Gate Array T-Box/T-1-Box 

摘      要：This work presents an efficient implementation of the AES (Advance Encryption Standard) based on T-box/T-1-box design for both the encryption and decryption on FPGA (Field Programmable Gate Array). The proposed architecture not only make efficient use of full capacity of dedicated 32 Kb BRAM (Block RAM) of latest Xilinx FPGAs (Virtex-5, Virtex-6 and 7 Series) but also saves considerable amount of BRAM and logical resources by using multiple accesses from single BRAM in one cycle of system clock as compared to conventional LUT (Look-Up-Table) techniques. The proposed T-box/T-1-box based AES design for both the encryption and decryption fits into just 4 BRAMs on FPGA and results in good efficiency TPS (Throughput per Slice) with less power consumption.