An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors

作     者：Kong, Joonho Koushanfar, Farinaz Chung, Sung Woo 

作者机构：Kyungpook Natl Univ Sch Elect Engn Taegu 702701 South Korea Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA Korea Univ Dept Comp & Radio Commun Engn Seoul 136713 South Korea 

出 版 物：《IEEE TRANSACTIONS ON COMPUTERS》 (IEEE Trans Comput)

年 卷 期：2015年第64卷第9期

页      面：2460-2475页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：National Research Foundation of Korea (NRF) - Ministry of Science, Education, and Technology [NRF-2012R1A2A2A01013816] Samsung Electronics ARO STIR [W911NF-14-1-0456] National Science Foundation (NSF) [CCF-1116858] ONR [N0001411-1-0885] Division of Computing and Communication Foundations Direct For Computer & Info Scie & Enginr Funding Source: National Science Foundation 

主　　题：3D microprocessor last-level cache leakage energy optimization narrow-width value process variation yield 

摘      要：As process technologies evolves, tackling process variation problems is becoming more challenging in 3D (i.e., die- stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3D microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3D microprocessors. In this paper, we propose a novel cache architecture that exploits narrow-width values for yield improvement of LLCs (in this paper, L2 caches) in 3D microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy- efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.