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International Conference on Integrated Circuit design and Technology (ICICdT)

作者： Kong, Joonho Chung, Sung Woo Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA Korea Univ Dept Comp & Radio Commun Engn Seoul 136713 South Korea

ISBN: (纸本)9781467347433

Process variation is one of the most challenging problems for 3d microprocessors. This is because stacked dies are likely to have fairly different characteristics due to wafer-to-wafer (W2W) variations, which may severely hurt yield of 3d microprocessors. In this paper, we introduce a process variation-tolerant 3d microprocessor design that exploits an architectural insight: narrow-width values. The main target of our technique is last-level caches (LLCs), which are composed of several dies. By storing only the meaningful bit parts within a data word into the LLCs while discarding the zero bit parts (which can be recovered by the zero-extension logic), our proposed technique improves a storage efficiency of the LLCs, which eventually enhances cache yield. According to our evaluation results, our technique significantly improves cache yield in a performance-/energy-efficient manner.

关键词： 3d microprocessor last-level cache narrow-width value process variation yield

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An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3d microprocessors

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IEEE TRANSACTIONS ON COMPUTERS 2015年第9期64卷 2460-2475页

作者： Kong, Joonho Koushanfar, Farinaz Chung, Sung Woo Kyungpook Natl Univ Sch Elect Engn Taegu 702701 South Korea Rice Univ Dept Elect & Comp Engn Houston TX 77005 USA Korea Univ Dept Comp & Radio Commun Engn Seoul 136713 South Korea

As process technologies evolves, tackling process variation problems is becoming more challenging in 3d (i.e., die- stacked) microprocessors. Process variation adversely affects performance, power, and reliability of the 3d microprocessors, which in turn results in yield losses. In particular, last-level caches (LLCs: L2 or L3 caches) are known as the most vulnerable component to process variation in 3d microprocessors. In this paper, we propose a novel cache architecture that exploits narrow-width values for yield improvement of LLCs (in this paper, L2 caches) in 3d microprocessors. Our proposed architecture disables faulty cache subparts and turns on only the portions that store meaningful data in the cache arrays, which results in high energy- efficiency as well as high cache yield. In an energy-/performance-efficient manner, our proposed architecture significantly recovers not only SRAM cell failure-induced yield losses but also leakage-induced yield losses.

关键词： 3d microprocessor last-level cache leakage energy optimization narrow-width value process variation yield

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Recent progress in 3d integration technology

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IEICE ELECTRONICS EXPRESS 2015年第7期12卷 20152001-20152001页

作者： Koyanagi, Mitsumasa Tohoku Univ New Ind Creat Hatchery Ctr Aoba Ku Sendai Miyagi 9808579 Japan

3d integration technology is the key for future LSIs with high-performance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3d integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3d integration technology has been discussed representing typical examples of heterogeneous 3d LSIs after the present situation of 3d integration technology is described.

关键词： 3d integration TSV heterogeneous integration 3d dRAM 3d image sensor 3d microprocessor

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Exploiting Narrow-Width Values for Process Variation-Tolerant 3-d microprocessors 12

Exploiting Narrow-Width Values for Process Variation-Toleran...

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49th ACM/EdAC/IEEE design Automation Conference (dAC)

作者： Kong, Joonho Chung, Sung Woo Korea Univ Dept Comp & Radio Commun Engn Seoul 136713 South Korea

ISBN: (纸本)9781450311991

Process variation is a challenging problem in 3d microprocessors, since it adversely affects performance, power, and reliability of 3d microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3d microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naive way-reduction scheme (that simply discards faulty cache lines), respectively.

关键词： 3d microprocessor Last-level cache Narrow-width value Process variation Yield

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