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内蒙古自治区呼和浩特市赛罕区大学西街235号 邮编: 010021
作者机构:Hefei Univ Technol Sch Comp Sci & Informat Engn Hefei 230601 Anhui Peoples R China Xidian Univ Sch Artificial Intelligence Xian 710071 Shaanxi Peoples R China Northwest Univ Sch Informat Sci & Technol Xian 710069 Shaanxi Peoples R China
出 版 物:《MICROELECTRONICS JOURNAL》 (微电子学杂志)
年 卷 期:2019年第83卷
页 面:131-136页
核心收录:
学科分类:0808[工学-电气工程] 0809[工学-电子科学与技术(可授工学、理学学位)] 08[工学] 0805[工学-材料科学与工程(可授工学、理学学位)]
基 金:NSFC [61802105, 61701403, 61672404, 61632019, 61751310, 61472301, 61875157, 61572387] Fundamental Research Funds of the Central Universities of China [2192018JZ2018HGBZ0154, SA-ZD160203, JBG160228, JBG160213, K5051399020, K5051202050] China Postdoctoral Science Foundation [2018M643719] Scientific Research Program - Shaanxi Provincial Education Department [18JK0767] Natural Science Basic Research Plan in Shaanxi Province of China [2017JQ6006, 2016ZDJC-08]
主 题:Distributed arithmetic Digital filter Convolution Hardware realization VLSI
摘 要:Distributed Arithmetic (DA) is a classic technique for the hardware realization of digital filters. We present a novel parallel arithmetic operation to overcome two drawbacks in existing DA and DA-based methods: 1) the throughput is difficult to improve and 2) hardware resource consumption increases exponentially with the length of filter order. The fundamental difference between the proposed and existing methods is that the proposed method factors the filter coefficients to find several simple basic operations, which can circumvent the inherent bit-serial nature of DA methods and achieve the whole operation in one clock cycle. Additionally, the number of possible basic operations increases linearly with the length of filter order, which means we can relieve the exponentially increasing hardware resource consumption. The proposed method is evaluated through two experiments, and the results demonstrate that the proposed technique outperforms existing DA and DA-based methods in terms of throughput and resource consumption.