A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder

作     者：Tan, LK Putnam, JS Lu, F D'Luna, LJ Mueller, DW Kindsfater, KR Cameron, KB Joshi, RB Hawley, RA Samueli, H 

作者机构：Broadcom Corp Irvine CA 92618 USA 

出 版 物：《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 (IEEE J Solid State Circuits)

年 卷 期：1998年第33卷第12期

页      面：2205-2218页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

主　　题：CMOS integrated circuits analogue-digital conversion decoding forward error correction quadrature amplitude modulation receivers telecommunication cables 0.5 micron 1.8 W 10 bit 5 V 70 Mbit/s ADC FEC decoder IF signal digitization adaptive equalization a Forward error correction DECODING FEC Regimen quadrature amplitude modulation signal analog digital converter Analog-digital conversion telecommunication cables Receivers Integrated circuits adaptive equalization CMOS integrated circuits Quadrature amplitude modulation 

摘      要：A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrated 10 b analog-to-digital converter (ADC) and forward error correction (FEC) decoder is presented. The chip accepts an analog 2 V-pp differential QAM signal centered at an intermediate frequency. The integrated 10 b ADC digitizes the IF signal, and all subsequent signal processing, including demodulation, timing/carrier recovery, adaptive equalization, and FEC, is performed digitally. The receiver IC is capable of receiving 4, 16, 32, 64, 128, 256, and 1024-QAM modulation formats. The 0.5-mu m triple level metal N-well CMOS chip has a complexity of 650 k transistors with a core area of 4.9 x 4.9 mm(2). Power dissipation is 1.8 W at 7 MBaud and 5 V.