Forward error correction (fec) is a critical component in communication systems as the errors induced by noisy channels can be corrected using the redundancy in the coded message. This paper introduces a novel multi-m...
详细信息
ISBN:
(纸本)9781450393546
Forward error correction (fec) is a critical component in communication systems as the errors induced by noisy channels can be corrected using the redundancy in the coded message. This paper introduces a novel multi-mode fec decoder accelerator that can decode Turbo, LDPC, and Polar codes using a unified architecture. The proposed design explores the similarities in these codes to enable energy efficient decoding with minimal overhead in the total area of the unified architecture. Moreover, the proposed design is highly reconfigurable to support various existing and future fec standards including 3GPP LTE/5G, and IEEE 802.11n WiFi. Implemented in GF 12nm FinFET technology, the design occupies 8.47mm(2) of chip area attaining 25% logic and 49% memory area savings compared to a collection of single-mode designs. Running at 250MHz and 0.8V, the decoder achieves per-iteration throughput and energy efficiency of 690Mb/s and 44pJ/b for Turbo;740Mb/s and 27.4pJ/b for LDPC;and 950Mb/s and 45.8pJ/b for Polar.
Since joint source-channel decoding is capable of exploiting the residual redundancy in the source signals for improving the attainable error resilience, it has attracted substantial attention. In this treatise, the a...
详细信息
Since joint source-channel decoding is capable of exploiting the residual redundancy in the source signals for improving the attainable error resilience, it has attracted substantial attention. In this treatise, the authors study iterative source-channel decoding (ISCD) aided video communications, where the video signal redundancy is modelled by a first-order Markov process. Firstly, the authors derive reduced-complexity formulas for the first-order Markov modelling (FOMM) aided source decoding. Then they propose a bit-based iterative horizontal-vertical scanline model (IHVSM) aided source decoding algorithm, where a horizontal and a vertical source decoder are employed for exchanging their extrinsic information using the iterative decoding philosophy. The iterative IHVSM aided decoder is then employed in a forward error correction (fec) encoded uncompressed video transmission scenario, where the IHVSM and the fec decoder exchange softbit-information for performing turbo-like ISCD for the sake of improving the reconstructed video quality. Finally, the authors benchmark the attainable system performance against a near-lossless H.264/AVC video communication system and the existing FOMM-based softbit source decoding scheme. The authors simulation results show that E-b/N-0 improvements in excess of 2.8 dB are attainable by the proposed technique in uncompressed video applications.
A DVB-C/ITU J.83-A compliant QAM (Quadrature Amplitude Modulation) demodulator suitable for digital cable TV is proposed, which can support 4 similar to 256QAM with variable bit rate up to 80Mbps. It integrates a 10-b...
详细信息
ISBN:
(纸本)0780387368
A DVB-C/ITU J.83-A compliant QAM (Quadrature Amplitude Modulation) demodulator suitable for digital cable TV is proposed, which can support 4 similar to 256QAM with variable bit rate up to 80Mbps. It integrates a 10-bit 40MSPS ADC, (204,188) Reed-Solomon decoder as well as a convolutional interleaver. The chip is implemented in SMIC 0.25um CMOS technology with die size of 3.50.5 mm(2). it features wide carrier offset acquisition range, robust demodulation algorithm and small circuit area.
A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrated 10 b analog-to-digital converter (ADC) and forward error correction (fec) decoder is presented. The chip accepts an a...
详细信息
A 70 Mb/s variable-rate 1024-quadrature amplitude modulated (QAM) cable receiver IC with integrated 10 b analog-to-digital converter (ADC) and forward error correction (fec) decoder is presented. The chip accepts an analog 2 V-pp differential QAM signal centered at an intermediate frequency. The integrated 10 b ADC digitizes the IF signal, and all subsequent signal processing, including demodulation, timing/carrier recovery, adaptive equalization, and fec, is performed digitally. The receiver IC is capable of receiving 4, 16, 32, 64, 128, 256, and 1024-QAM modulation formats. The 0.5-mu m triple level metal N-well CMOS chip has a complexity of 650 k transistors with a core area of 4.9 x 4.9 mm(2). Power dissipation is 1.8 W at 7 MBaud and 5 V.
暂无评论