Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture

作     者：Kwon, YS Kyung, CM 

作者机构：Korea Adv Inst Sci & Technol CHiPS VLSI Syst Lab Taejon 305701 South Korea 

出 版 物：《MICROPROCESSORS AND MICROSYSTEMS》 (微处理机与微型系统)

年 卷 期：2004年第28卷第5-6期

页      面：341-350页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：field-programmable gate arrays interconnection architecture time-multiplexing scheduling 

摘      要：The gate utilization of FPGAs and speed of emulation in multi-FPGA system are limited by the interconnection architecture and the number of pins. The time-multiplexing of interconnection wires is required for multi-FPGA systems incorporating several state-of-the-art FPGAs. This article proposes a circuit partitioning algorithm called SCheduling driven Algorithm for TOMi (SCATOMi) for multi-FPGA systems with interconnection architecture called Time-multiplexed, Off chip, Multi-casting interconnection (TOMi). SCATOMi improves the performance of the TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2-81.3% while the critical path delay is reduced to 46.1-67.6% compared to traditional architectures. (C) 2004 Elsevier B.V. All rights reserved.