The design of a SRAM-based field-programmable gate array -: Part II:: Circuit design and layout

作     者：Chow, P Seo, SO Rose, J Chung, K Páez-Monzón, G Rahardja, I 

作者机构：Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada ATI Technol Thornhill ON L3T 7N6 Canada Xilinx Toronto Dev Ctr Toronto ON M5S 2T9 Canada Natl Semicond Corp Cyrix W Santa Clara CA 95052 USA Aristo Technol Inc Cupertino CA 95104 USA 

出 版 物：《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》 (IEEE Trans Very Large Scale Integr VLSI Syst)

年 卷 期：1999年第7卷第3期

页      面：321-330页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：FPGA FPGA architecture FPGA circuit design field-programmable gate arrays SRAM programmable 

摘      要：Field-programmable gate arrays (FPGA s) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static random-access memory programmable FPGA, This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs hi the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive, We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. Thtr minitile is replicated in a 4 x 4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias, This technique al;so permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture.