REMARC: Reconfigurable multimedia array coprocessor

作     者：Miyamori, T Olukotun, K 

作者机构：Toshiba Corp Kawasaki Kanagawa 2108520 Japan Stanford Univ Fac Elect Engn Stanford CA 94305 USA 

出 版 物：《IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS》 (电子信息通信学会汇刊：信息与系统)

年 卷 期：1999年第E82D卷第2期

页      面：389-397页

核心收录：

学科分类：0810[工学-信息与通信工程] 08[工学] 0835[工学-软件工程] 081001[工学-通信与信息系统] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：computer architecture reconfigurable computer array processor multimedia application 

摘      要：This paper describes a new reconfigurable processor architecture called REMARC (Reconfigurable Multimedia Array Coprocessor). REMARC is a small array processor that is tightly coupled to a main RISC processor. It consists of a global control unit and 64 16-bit processors called nano processors. REMARC is designed to accelerate multimedia applications, such as video compression, decompression, and image processing. These applications typically use 8-bit or 16-bit data therefore, each nano processor has a 16-bit datapath that is much wider than those of other reconfigurable coprocessors. We have developed a programming environment for REMARC and several realistic application programs, DES encryption, MPEG-2 decoding, and MPEG-2 encoding. REMARC can implement various parallel algorithms which appear in these multimedia applications. For instance, REMARC can implement SIMD type instructions similar to multimedia instruction extensions for motion compensation of the MPEG-2 decoding. Furthermore, the highly pipelined algorithms, like systolic algorithms, which appear in motion estimation of the MPEG-2 encoding can also be implemented efficiently. REMARC achieves speedups ranging from a factor of 2.3 to 21.2 over the base processor which is a single issue processor or a-issue superscalar processor. We also compare its performance with multimedia instruction extensions. Using more processing resources, REMARC can achieve higher performance than multimedia instruction extensions.