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array processor FOR BLOCK ADAPTIVE LS FIR FILTERING

SIGNAL PROCESSING 1994年第1-2期39卷 215-222页

作者： NIKOLAIDIS, SS THEODORIDIS, S GOUTIS, CE VLSI Design Laboratory Department of Electrical Engineering University of Patras 26110 Patras Greece VLSI Design Laboratory Department of Computer Engineering University of Patras 26110 Patras Greece

In this paper the architecture for the realization of a new, highly-parallel, block-type, order recursive algorithm for LS FIR filtering is introduced. A linear array of p processing elements is used, implementing this algorithm for p order in linear time, O(p). Using a suitable scheduling of the algorithm and a pipeline divider, a three fold reduction of hardware is achieved, without significant degradation in time performance, compared to the fully parallel realization. Furthermore, the computation of the correction sums, needed for the initialization of the system, is performed on the existing linear array resulting in additional hardware saving.

关键词： LEAST SQUARE FIR FILTERING BLOCK ADAPTIVE PROCESSING array processor

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A high speed multi-level-parallel array processor for vision chips

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Science China(Information Sciences) 2014年第6期57卷 211-222页

作者： SHI Cong YANG Jie WU NanJian WANG ZhiHua State Key Laboratory for Superlattices and Microstructures Institute of SemiconductorsChinese Academy of Sciences Department of Electronic Engineering Tsinghua University Institute of Microelectronics Tsinghua University

This paper proposes a high speed multi-level-parallel array processor for programmable vision *** processor includes 2-D pixel-parallel processing element(PE)array and 1-D row-parallel row processor(RP)*** two arrays both operate in a single-instruction multiple-data(SIMD)fashion and share a common instruction *** sizes of the arrays are scalable according to dedicated *** PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal *** connection can help to speed up local operations in low-level image *** the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP *** array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED *** results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.

关键词： vision chip array processor multi-level-parallel high speed image processing face detection

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New VLSI array processor design for image window operations

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 1999年第5期46卷 635-640页

作者： Li, DJ Jiang, L Isshiki, T Kunieda, H Tokyo Inst Technol Dept Elect & Elect Engn Meguro Ku Tokyo Japan

A novel architecture named Window-Memory Sharing processor array is proposed, which targets window operations in image processing. The architecture can be used not only for conventional image filtering, but also in practical window operations such as motion vector search in MPEG2. The derived architecture is flexible enough to satisfy user's requirement for either area or speed.

关键词： array processor block matching image processing systolic array window operation

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Fixed-point error analysis and an efficient array processor design of two-dimensional sliding DFT

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SIGNAL PROCESSING 1999年第3期73卷 191-201页

作者： Zhu, YS Zhou, H Gu, H Wang, ZZ Shanghai Jiao Tong Univ Dept Biomed Engn Shanghai 200030 Peoples R China

Two-dimensional (2-D) sliding discrete Fourier transform (DFT) algorithm can realize sliding spectrum analysis and real-time signal processing. In this paper, its fixed-point error analysis is carried out to form a theoretical basis for hardware implementation. The analysis models the error as an additive white noise and arrives at the signal to noise ratio (SNR) successively. Then, a simplified method for 2-D sliding DTT based on vector radix (VR) algorithm is introduced. With this approach the fixed-point error can be reduced to the same scale as that of 2-D FFT. As an example, the architecture and error analysis of 8*8 2-D sliding DFT array processor based on VR-4*4 algorithm are presented. The idea can be extended to larger size DFT. Finally some comparisons ape derived. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： sliding DFT error analysis array processor

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Design optimization of VLSI array processor architecture for window image processing

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1999年第8期E82A卷 1475-1484页

作者： Li, DJ Jiang, L Kunieda, H Tokyo Inst Technol Dept Elect & Elect Engn Tokyo 1528552 Japan

In this paper;we present a novel architecture named as Window-MSPA architecture which targets to window operations in image processing. We have previously developed a Memory Sharing processor array (MSPA) for fast array processing with regular iterative algorithms. Window-MSPA tries to optimize the data I/O ports and the number of processing elements so as to reduce hardware cost. The input scheme of image data is restricted to row by row input which simplifies the I/O architecture. Under this practical I/O restriction, the fastest processings are achieved. In this paper, we present the general Window-MSPA design methodology for wide variety of applications.,its an practical application, we have already reported the design of MP@HL MPEG2 Motion Estimator LS1[13]. Design formulas for Window-MSPA architecture are given for various size of window: operations in image processing. Thus, the derived architecture is flexible enough to satisfy user's requirement for either area or speed.

关键词： image processing array processor window operation systolic array

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A VERSATILE MECHANISM TO MOVE DATA IN AN array processor

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IEEE TRANSACTIONS ON COMPUTERS 1985年第6期34卷 506-522页

作者： LENFANT, J IRISA UniversitÃ© de Rennes Campus de Beaulieu 3504 Rennes Cedex France. Abstract Authors References Cited By Keywords Metrics Similar Download Citation Email Print Request Permissions

Selection of elements and alignment of operands are fundamental operations on data, just as are arithmetic operations. Whereas sophisticated algorithms have been devised for the latter, vector processors usually lack a flexible and efficient routing unit. This is especially true of SIMD computers, to which the present study is devoted. Examples of required manipulations are: transfer, shift, diffusion, compression, expansion, mesh, perfect shuffle, and bit reversal. Using a method described in a previous paper of ours [15] we present algorithms to control a Benes network and perform these manipulations on vectors whose length is equal to the number of processing elements. Then we dispense with this constraint and propose a mechanism to rearrange vectors of any size, stored according to several schemes.

关键词： APL language Benes network array processor parallel computer perfect shuffle signal processor switching network

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SPOKEN LANGUAGE RECOGNITION ON A DSP array processor

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第7期5卷 697-703页

作者： GLINSKI, S ROE, D AT and T Bell Laboratories Inc. Murray Hill NJ USA

A new architecture is presented to support the general class of real-time large-vocabulary speaker-independent continuous speech recognizers incorporating language models. Many such recognizers require multiple high-performance central processing units (CPU's) as well as high interprocessor communication bandwidth. This array processor provides a peak CPU performance of 2.56 giga-floating point operations per second (GFLOPS) as well as a high-speed communication network. In order to efficiently utilize these resources, algorithms were devised for partitioning speech models for mapping into the array processor. Also, a novel scheme is presented for a functional partitioning of the speech recognizer computations. The recognizer is functionally partitioned into six stages, namely, the linear predictive coding (LPC) based feature extractor, mixture probability computer, (phone) state probability computer, word probability computer, phrase probability computer, and traceback computer. Each of these stages is further subdivided as many times as necessary to fit the individual processing elements (PE's). The functional stages are pipelined and synchronized with the frame rate of the incoming speech signal. This partitioning also allows a multistage stack decoder to be implemented for reduction of computation. The fully configured array processor is composed of 128 PE's, each of which comprises a floating point digital signal processor, a local memory of 64-kilobyte by 32-bit words, and a custom communications device that permits each PE to talk with four adjacent PE's in a 2-D grid. A second communication network provides global communication between a host processor and each PE. Each node is programmable in the high-level C language. One recognizer we have implemented at AT&T uses 1759 phonelike units (PLU's). These units comprise phones, di hones, and triphones that are selected based on their frequency of occurrence in the training corpus. Each PLU is modeled with a thr

关键词： array processor DIGITAL SIGNAL processorS FUNCTIONAL DECOMPOSITION GRAMMAR PARTITION MESSAGE-PASSING ARCHITECTURE processor UTILIZATION SPEECH RECOGNITION

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A complete system for NN classification based on a VLSI array processor

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PATTERN RECOGNITION 2000年第12期33卷 2083-2093页

作者： Ferrari, A Borgatti, M Guerrieri, R PARADES GEIE I-00186 Rome Italy STMicroelect Cent Res & Dev Innovat Syst Design Grp Agrate Brianza Italy Univ Bologna DEIS I-40136 Bologna Italy

This paper describes a VLSI array processor system designed and built for classification problems based on the k-nearest-neighbors approach. This architecture is suitable for different pattern recognition applications and is very efficient for high-dimensional databases. The architecture is scalable with the size of the recognition problem making the system effectively applicable to computational intensive application like on-line pattern recognition. A system prototype composed of a board with two processors, the software driver and a test application have been built and evaluated. For handwritten character recognition task the complete system shows a speed up of 260 times over a sequential algorithm running on a Sun SPARC20 workstation. (C) 2000 Pattern Recognition Society. Published by Elsevier Science Ltd. All rights reserved.

关键词： pattern classification k-nearest neighbors array processor configurable architecture VLSI

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Design and Implementation of Memory Access Fast Switching Structure in Cluster-Based Reconfigurable array processor

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Journal of Beijing Institute of Technology 2017年第4期26卷 494-504页

作者： Rui Shan Lin Jiang Junyong Deng Xueting Li Xubang Shen School of Micro-electronics Xidian University Xi' an 710071 China School of Electronic Engineering Xi'an University of Posts and Telecommunication Xi'an 710121 China School of Computer Science & Technology Xi' an University of Posts and Telecommunication Xi' an 710121 China

Memory access fast switching structures in cluster are studied,and three kinds of fast switching structures（ FS,LR2 SS,and LAPS） are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT,FFT,SAD,IME,FME,and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures,our proposed structures have lower data access delay and lower area.

关键词： array processor distributed memory memory access switching structure

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MEMORY AND BUS CONFLICT IN AN array processor

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IEEE TRANSACTIONS ON COMPUTERS 1977年第6期26卷 514-521页

作者： NUTT, GJ UNIV COLORADO DEPT COMP SCIBOULDERCO 80302

The multiassociative processor (MAP) system is a hypothetical machine composed of eight control units (CU"s) and an arbitrary number of processing elements (PE"s). Each CU is allocated a subset of the identical PE"s in order to process a single-instruction-stream-multiple-data-stream program. The eight CU"s must be able to access a common main memory system and transmit data to subsets of the PE"s over a shared data bus system. This paper discusses the analysis of these two components of the system where this analysis relies heavily on three simulation programs. The first program interprets assembly language programs for the hypothetical machine and the other two programs model the memory system and the data bus system. The interpreter is driven by both realistic array processor programs and synthetic programs designed specifically to test the components of the system.

关键词： array processor associative processor design evaluation multiprocessor SIMD simulation trace driven simulation.

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