咨询与建议

看过本文的还看了

相关文献

该作者的其他文献

文献详情 >Design optimization of VLSI ar... 收藏

Design optimization of VLSI array processor architecture for window image processing

作     者:Li, DJ Jiang, L Kunieda, H 

作者机构:Tokyo Inst Technol Dept Elect & Elect Engn Tokyo 1528552 Japan 

出 版 物:《IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES》 (电子信息通信学会汇刊:电子学、通信及计算机科学基础)

年 卷 期:1999年第E82A卷第8期

页      面:1475-1484页

核心收录:

学科分类:0808[工学-电气工程] 0809[工学-电子科学与技术(可授工学、理学学位)] 08[工学] 0812[工学-计算机科学与技术(可授工学、理学学位)] 

主  题:image processing array processor window operation systolic array 

摘      要:In this paper;we present a novel architecture named as Window-MSPA architecture which targets to window operations in image processing. We have previously developed a Memory Sharing Processor Array (MSPA) for fast array processing with regular iterative algorithms. Window-MSPA tries to optimize the data I/O ports and the number of processing elements so as to reduce hardware cost. The input scheme of image data is restricted to row by row input which simplifies the I/O architecture. Under this practical I/O restriction, the fastest processings are achieved. In this paper, we present the general Window-MSPA design methodology for wide variety of applications.,its an practical application, we have already reported the design of MP@HL MPEG2 Motion Estimator LS1[13]. Design formulas for Window-MSPA architecture are given for various size of window: operations in image processing. Thus, the derived architecture is flexible enough to satisfy user s requirement for either area or speed.

读者评论 与其他读者分享你的观点

用户名:未登录
我的评分