VLSI architecture for quadtree-based fractal image coding

作     者：Lee, S Omachi, S Aso, H 

作者机构：Tohoku Univ Grad Sch Engn Dept Elect & Commun Engn Aoba Ku Sendai Miyagi 9808579 Japan 

出 版 物：《IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES》 (IEE Proc Comput Digital Tech)

年 卷 期：2001年第148卷第4-5期

页      面：141-146页

核心收录：

主　　题：Pattern recognition and computer vision equipment smallest range blocks fractals Combinatorial mathematics fast comparison module VLSI architecture VLSI isometric transformations File organisation local data communication flexible-size fractal image coding Graphics techniques Semiconductor integrated circuits Computer vision and image processing techniques large domain blocks image coding quadtrees quadtree partitioning Signal processing and conditioning equipment and techniques distortion image processing equipment Image and video coding neighbouring processors small domain blocks quadtree based fractal image coding Signal processing theory 

摘      要：A VLSI architecture for flexible-size fractal image coding is proposed. The main features of this architecture are that it is capable of performing fractal image coding based on quadtree partitioning without the external memory for the fixed domain pool and uses only local data communication. Since large domain blocks consist of small domain blocks, the calculations of distortion for all kinds of domain block are performed using only the domain pool, which is extracted from the smallest range blocks of the neighbouring processors. This architecture has a fast comparison module which can compute the distortions between a range block and the eight isometric transformations of domain blocks by one full rotation around the centre.