Cache-coherent distributed shared memory: Perspectives on its development and future challenges

作     者：Hennessy, J Heinrich, M Gupta, A 

作者机构：Stanford Univ Comp Syst Lab Stanford CA 94305 USA Cornell Univ Sch Elect Engn Ithaca NY 14853 USA Microsoft Inc Microsoft Res Redmond WA 98052 USA 

出 版 物：《PROCEEDINGS OF THE IEEE》 (电气与电子工程师学会会报)

年 卷 期：1999年第87卷第3期

页      面：418-429页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 

基　　金：Defense Advanced Research Projects Agency  DARPA 

主　　题：cache coherence directory-based cache coherence distributed shared memory multiprocessor architecture scalable multiprocessors 

摘      要：Distributed shared memory is an architectural approach that allows multiprocessors to support a single shared address space that is implemented with physically distributed memories. Hardware-supported distributed shared memory is becoming the dominant approach for building multiprocessors with moderate to large numbers of processors. Cache coherence allows such architectures to use caching to take advantage of locality in applications without changing the programmer s model of memory. We review the key developments that led to the creation of cache-coherent distributed shared memory and describe the Stanford DASH multiprocessor, the first working implementation of hardware-supported scalable cache coherence. We then provide a perspective on such architectures and discuss important remaining technical challenges.