A binary link tracker for the <i>BaBar</i> Level 1 trigger system

作     者：Berenyi, A Chen, HK Dao, K Dow, SF Gehrig, SK Gill, MS Grace, C Jared, RC Johnson, JK Karcher, A Kasen, D Kirsten, FA Kral, JF LeClerc, CM Levi, ME von der Lippe, H Liu, TH Marks, KM Meyer, AB Minor, R Montgomery, AH Romosan, A 

作者机构：EO Lawrence Berkeley Natl Lab Berkeley CA 94720 USA 

出 版 物：《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》 (IEEE Trans Nucl Sci)

年 卷 期：1999年第46卷第4期

页      面：928-932页

核心收录：

学科分类：0808[工学-电气工程] 08[工学] 0827[工学-核科学与技术] 

基　　金：Division of High Energy Physics U.S. Department of Energy, USDOE, (DE-AC03-76SF00098) U.S. Department of Energy, USDOE Alexander von Humboldt-Stiftung 

主　　题：drift chambers Binary Field programmable gate arrays B mesons CP violation very high density lipoproteins 

摘      要：The BABAR detector at PEP-II will operate in a high-luminosity e(+)e(-) collider environment near the Y(4S) resonance with the primary goal of studying CP violation in the B meson system. In this environment, typical physics events of interest involve multiple charged particles. These events are identified by counting these tracks in a fast first level (Level 1) trigger system, by reconstructing the tracks in real time. For this purpose, a Binary Link Tracker Module (BLTM) was designed and fabricated for the BABAR Level 1 Drift Chamber trigger system. The BLTM is responsible for linking track segments, constructed by the Track Segment Finder Modules (TSFM), into complete tracks. A single BLTM module processes a 360 MBytes/s: stream of segment hit data, corresponding to information from the entire Drift chamber, and implements a fast and robust algorithm that tolerates high hit occupancies as well as local inefficiencies of the Drift Chamber. The algorithms and the necessary control logic of the BLTM were implemented in Field Programmable Gate Arrays (FPGAs), using the VHDL hardware description language. The finished 9U x 400 nun Euro-format board contains roughly 75,000 gates of programmable logic or about 10,000 lines of VHDL code synthesized into five FPGAs.