FPGA-based configurable systolic architecture for window-based image processing

作     者：Torres-Huitzil, C Arias-Estrada, M 

作者机构：Natl Inst Astrophys Opt & Electron Dept Comp Sci Puebla 72000 Mexico 

出 版 物：《EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING》 (EURASIP信号处理进展杂志)

年 卷 期：2005年第2005卷第7期

页      面：1024-1034页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：FPGA configurable system real time window-based image processing systolic array 

摘      要：Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of 7 x 7 configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to 7 x 7, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7 X 7 generic window-based operators on 512 x 512 gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.